source: anr/anr.bib @ 94

Last change on this file since 94 was 93, checked in by coach, 15 years ago

Fixed anr.bib with most missing references
File size: 23.1 KB
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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% LIP6
3% HPC
4@InProceedings{hpc06a,
5  author    = {{M.B. Gokhale and al.}},
6  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
7  booktitle = {Systems and Algorithms, CSREA Press},
8  pages     = {11-20},
9  year      = {2006},
10}
11@MISC{hpc06b,
12  author =       {{D. Buell}},
13  title  =   {{Programming Reconfigurable Computers}},
14  booktitle = {Summer Institute},
15  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
16  year =         {2006},
17}
18@InProceedings{hpc07a,
19  author =       {{T. Van Court and al.}},
20  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
21  booktitle = {Computer, vol. 40, no. 3},
22  pages     = {50-57},
23  month     = {mars},
24  year =         {2007},
25}
26@misc{hpc08,
27  title        = {Mitrionics},
28  howpublished = {http://www.mitrionics.com/},
29  year         = {2009},
30}
31@misc{hpc09,
32  title        = {Gidel},
33  howpublished = {http://www.gidel.com/},
34  year         = {2009},
35}
36@misc{hpc10,
37  title        = {Convey Computer},
38  howpublished = {http://www.conveycomputers.com/},
39  year         = {2009},
40}
41@InProceedings{hpc11,
42  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
43  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
44  booktitle = {HPRCTA},
45  year =         {2008},
46}
47@InProceedings{hpc12,
48  author =       {{P. Lysaght and J. Dunlop}},
49  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
50  booktitle = {Field Programmable Logic and Applications, Oxford, England},
51  month     = {Sept},
52  year =         {1993},
53}
54
55
56% System design
57@misc{soclib,
58  title        = {Soclib},
59  howpublished = {http://www.soclib.fr/},
60  year         = {2009},
61}
62
63@misc{system-generateur-for-dsp,
64  title        = {{System Generator for DSP}},
65  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
66  year         = {2009},
67}
68
69@misc{spoc-builder,
70  title        = {{sopc builder support}},
71  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
72  year         = {2009},
73}
74
75@InProceedings{disydent05,
76  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}},
77  title =        {{Platform-based design from parallel C specifications}},
78  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
79  pages     = {1811--1826},
80  month     = {December},
81  year =         {2005},
82}
83
84% HLS
85% http://mesl.ucsd.edu/spark/index.shtml
86@BOOK{spark04,
87  author     = {S. Gupta and al.},
88  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
89  publisher  = {Springer},
90  year       = {2004},
91}
92
93
94@INBOOK{ugh08,
95  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
96  title     = {User Guided High Level Synthesis},
97  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
98  publisher = {Springer},
99  chapter   = {10},
100  year      = {2008},
101}
102
103@misc{pico,
104  title        = {{PICO}},
105  howpublished = {http://www.synfora.com/},
106  year         = {2009},
107}
108
109@misc{catapult-c,
110  title        = {{CATAPULT-C Mentor HLS tool}},
111  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
112  year         = {2009},
113}
114
115@misc{cynthetizer,
116  title        = {{Forte's CYNTHESIZER}},
117  howpublished = {http://www.forteds.com/},
118  year         = {2009},
119}
120
121
122
123%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
124%%% UBS
125
126
127@INBOOK{gaut08,
128  author    = {P. Coussy and al.},
129  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
130  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
131  publisher = {Springer},
132  year      = {2008},
133}
134
135@article{DBLP:journals/dt/CoussyT09,
136  author    = {Philippe Coussy and
137               Andres Takach},
138  title     = {Guest Editors' Introduction: Raising the Abstraction Level
139               of Hardware Design},
140  journal   = {IEEE Design {\&} Test of Computers},
141  volume    = {26},
142  number    = {4},
143  year      = {2009},
144  pages     = {4-6},
145  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
146  bibsource = {DBLP, http://dblp.uni-trier.de}
147}
148
149
150@article{DBLP:journals/dt/CoussyGMT09,
151  author    = {Philippe Coussy and
152               Daniel D. Gajski and
153               Michael Meredith and
154               Andres Takach},
155  title     = {An Introduction to High-Level Synthesis},
156  journal   = {IEEE Design {\&} Test of Computers},
157  volume    = {26},
158  number    = {4},
159  year      = {2009},
160  pages     = {8-17},
161  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
162  bibsource = {DBLP, http://dblp.uni-trier.de}
163}
164
165
166@article{DBLP:journals/vlsisp/ThabetCHM09,
167  author    = {Farhat Thabet and
168               Philippe Coussy and
169               Dominique Heller and
170               Eric Martin},
171  title     = {Exploration and Rapid Prototyping of DSP Applications using
172               SystemC Behavioral Simulation and High-level Synthesis},
173  journal   = {Signal Processing Systems},
174  volume    = {56},
175  number    = {2-3},
176  year      = {2009},
177  pages     = {167-186},
178  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
179  bibsource = {DBLP, http://dblp.uni-trier.de}
180}
181
182
183
184@inproceedings{CHAVET:2007:HAL-00153994:1,
185        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
186        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
187        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
188        language = {{A}nglais},
189        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
190        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
191        publisher = {{L}ibrary of {C}ongress },
192        pages = {2946 },
193        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
194        editor = {{IEEE} },
195        note = {{ISBN}:1-4244-0921-7 },
196        audience = {internationale },
197    day = {28},
198    month = {05},
199    year = {2007},
200    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
201    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
202}
203
204
205@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
206  author    = {Cyrille Chavet and
207               Caaliph Andriamisaina and
208               Philippe Coussy and
209               Emmanuel Casseau and
210               Emmanuel Juin and
211               Pascal Urard and
212               Eric Martin},
213  title     = {A design flow dedicated to multi-mode architectures for
214               DSP applications},
215  booktitle = {ICCAD},
216  year      = {2007},
217  pages     = {604-611},
218  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
219  crossref  = {DBLP:conf/iccad/2007},
220  bibsource = {DBLP, http://dblp.uni-trier.de}
221}
222
223
224@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
225  author    = {Cyrille Chavet and
226               Philippe Coussy and
227               Pascal Urard and
228               Eric Martin},
229  title     = {A design methodology for space-time adapter},
230  booktitle = {ACM Great Lakes Symposium on VLSI},
231  year      = {2007},
232  pages     = {347-352},
233  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
234  crossref  = {DBLP:conf/glvlsi/2007},
235  bibsource = {DBLP, http://dblp.uni-trier.de}
236}
237
238
239@inproceedings{CHAVET:2007:HAL-00154025:1,
240        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
241        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
242        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
243        language = {{A}nglais},
244        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
245        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
246        publisher = {{E}urasip },
247        pages = {??? },
248        address = {{P}oznan {P}ologne },
249        audience = {internationale },
250    day = {03},
251    month = {09},
252    year = {2007},
253    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
254    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
255}
256
257
258@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
259        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
260        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
261        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
262        language = {{A}nglais},
263        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
264        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
265        publisher = {{AHS} },
266        pages = {7 },
267        address = {{E}dinburgh {R}oyaume-{U}ni },
268        audience = {internationale },
269    year = {2007},
270    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
271    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
272}
273
274
275@inproceedings{COUSSY:2005:HAL-00077301:1,
276        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
277        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
278        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
279        keywords = {{DSP} application, synthesis under memory and communication constraints},
280        language = {{A}nglais},
281        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
282        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
283        publisher = {{IEEE} },
284        pages = {{V}ol. {V} p. 61-64 },
285        editor = {{IEEEE} },
286    year = {2005},
287    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
288    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
289}
290
291
292
293%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
294%%%%% IRISA
295@InProceedings{KluterCodes08,
296  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
297  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
298  booktitle = {ISSS/CODES},
299  year =         {2008},
300}
301
302@InProceedings{KluterDAC09,
303  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
304  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
305  booktitle = {Design Automation Conference (DAC)},
306  year =         {2009},
307}
308
309@InProceedings{YuCodes04,
310  author =       {{Pan Yu and Tulika Mitra}},
311  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
312  booktitle = {ISSS/CODES},
313  year =         {2004},
314}
315
316@InProceedings{Dinh08,
317  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
318  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
319  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
320  year =         {2008},
321}
322
323@Misc{NIOS2UG,
324  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
325  year =         {2008},
326}
327
328%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
329%%% CITI
330@book{Polis,
331  author = {Balarin, Felice},
332  publisher = {Kluwer Academic Publishers},
333  title = {Hardware-software co-design of embedded systems : the POLIS
334        approach},
335  year = {1997}
336}
337
338@INPROCEEDINGS{Coware,
339  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
340                Rompaey and Steven Vercauteren and Diederik Verkest},
341  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
342  booktitle = {Proceedings of the IEEE},
343  year = {1997},
344  pages = {391--418}
345}
346
347@article{Jantsch,
348  author = {Mattias O'Nil and Axel Jantsch},
349  title = {Device Driver and DMA Controller Synthesis from HW/SW
350                        Communication protocol specifications},
351  journal = {Design Automation for Embedded Systems},
352  year = {2001},
353  volume = {6},
354  pages = {177-205}
355}
356
357@InProceedings{Park01,
358  author =   {Joonseok Park and Pedro C.~Diniz},
359  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
360                Data Applications on {FPGA}-Based Computing Engines},
361  booktitle =    {International Symposium on System Synthesis (ISSS)},
362  pages = {221-226},
363  year =     {2001},
364}
365
366@article{FR-vlsi,
367  author = {Antoine Fraboulet and Tanguy Risset},
368  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
369  journal = {Journal of VLSI Signal Processing},
370  publisher = {Springer Science},
371  year = {2007},
372  volume = {59},
373  pages = {73-85}
374}
375
376@InProceedings{jerraya,
377  author =   {Sungjoo Yoo and Jerraya Ahmed},
378  title =    {Introduction to Hardware Abstraction Layers for SoC},
379  OPTcrossref =  {},
380  OPTkey =   {},
381  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
382  pages =    {336 -- 337},
383  year =     2003,
384  OPTeditor =    {},
385  OPTvolume =    {},
386  OPTnumber =    {},
387  OPTseries =    {},
388  OPTaddress =   {},
389  OPTmonth =     {},
390  OPTorganization = {},
391  OPTpublisher = {},
392  OPTnote =      {},
393  OPTannote =    {}
394}
395
396@INPROCEEDINGS{FAUST,
397  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
398        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
399        P. Penard and  A. Bouttier and  F. Berens}, 
400  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
401  pages = {},
402  BOOKTITLE="ISSCC\'2007", 
403  year = {2007},
404  publisher = {IEEE Computer Society},
405  address = {San Francisco, USA},
406};
407
408@inproceedings{JerrayaPetrot,
409 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
410 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
411 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
412 year = {2006},
413 isbn = {1-59593-381-6},
414 pages = {280--285},
415 location = {San Francisco, CA, USA},
416 publisher = {ACM},
417 address = {New York, NY, USA},
418}
419
420@inproceedings{mwmr,
421 author = {E. Faure and A. Greiner and D. Genius},
422 title = {A generic hardware/software communication mechanism for
423          Multi-Processor System on Chip, Targeting Telecommunication Applications},
424 booktitle = {ReCoSoC'06},
425 year = {2006},
426 pages = {237--242},
427 address = {Montpellier, France}
428 }
429
430@inproceedings{Alberto,
431  author    = {Roberto Passerone and
432               James A. Rowson and
433               Alberto L. Sangiovanni-Vincentelli},
434  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
435  booktitle = {DAC},
436  year      = {1998},
437  pages     = {8-13}
438}
439
440@article{Avnit,
441  author    = {Karin Avnit and
442               Vijay D'Silva and
443               Arcot Sowmya and
444               S. Ramesh and
445               Sri Parameswaran},
446  title     = {Provably correct on-chip communication: A formal approach
447               to automatic protocol converter synthesis},
448  journal   = {ACM Trans. Design Autom. Electr. Syst.},
449  volume    = {14},
450  number    = {2},
451  year      = {2009}
452}
453
454@inproceedings{smith,
455  author    = {James Smith and
456               Giovanni De Micheli},
457  title     = {Automated Composition of Hardware Components},
458  booktitle = {DAC},
459  year      = {1998},
460  pages     = {14-19}
461}
462
463@inproceedings{Narayan,
464  author    = {Sanjiv Narayan and
465               Daniel Gajski},
466  title     = {Interfacing Incompatible Protocols Using Interface Process
467               Generation},
468  booktitle = {DAC},
469  year      = {1995},
470  pages     = {468-473}
471}
472
473@TECHREPORT{Ptolemy,
474  AUTHOR       = { E.A. Lee et al.},
475  INSTITUTION  = {University of California, Berkeley},
476  NUMBER       = {UCB/ERL No. M99/37},
477  TITLE        = {Overview of the Ptolemy Project},
478  YEAR         = {1999},
479  MONTH        = {july}
480}
481
482@article{syntol,
483    author={Paul Feautrier},
484    title={Scalable and Structured Scheduling},
485    journal={Int. J. of Parallel Programming},
486    year=2006,
487    month=May, number=5, volume=34,
488    pages="459--487"
489}
490
491@InProceedings{bee,
492  author={Christophe Alias and Fabrice Baray and Alain Darte},
493  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
494  booktitle = {LCTES},
495  year = {2007},
496  publisher = {ACM}
497}
498
499
500
501%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
502
503@inproceedings{DAC09,
504 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
505 title = {Way Stealing: cache-assisted automatic instruction set extensions},
506 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
507 year = {2009},
508 isbn = {978-1-60558-497-3},
509 pages = {31--36},
510 location = {San Francisco, California},
511 doi = {http://doi.acm.org/10.1145/1629911.1629923},
512 publisher = {ACM},
513 address = {New York, NY, USA},
514 }
515
516@inproceedings{CODES08,
517 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
518 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
519 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
520 year = {2008},
521 isbn = {978-1-60558-470-6},
522 pages = {243--248},
523 location = {Atlanta, GA, USA},
524 doi = {http://doi.acm.org/10.1145/1450135.1450191},
525 publisher = {ACM},
526 address = {New York, NY, USA},
527 }
528 
529@article{TVLSI06,
530        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
531 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
532 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
533 volume = {14},
534 number = {9},
535 year = {2006},
536 issn = {1063-8210},
537 pages = {986--997},
538 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
539 publisher = {IEEE Educational Activities Department},
540 address = {Piscataway, NJ, USA},
541}
542
543
544@Book{NIOS2,
545  title =        {{Nios II Processor Reference Handbook}},
546  publisher =    {Altera},
547  year =         {2009},
548}
549
550
551@inproceedings{ARC08,
552 author = {Galuzzi, Carlo and Bertels, Koen},
553 title = {The Instruction-Set Extension Problem: A Survey},
554 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
555 year = {2008},
556 isbn = {978-3-540-78609-2},
557 pages = {209--220},
558 location = {London, UK},
559 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
560 publisher = {Springer-Verlag},
561 address = {Berlin, Heidelberg},
562 }
563
564@inproceedings{CODES99,
565 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
566 title = {{A flexible code generation framework for the design of application specific programmable processors}},
567 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
568 year = {1999},
569 pages = {27--31},
570 location = {Rome, Italy},
571 publisher = {ACM},
572 address = {New York, NY, USA},
573 }
574
575@inproceedings{ASAP05,
576 author = {L'Hours, Ludovic},
577 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
578 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
579 year = {2005},
580 pages = {127--133},
581 publisher = {IEEE Computer Society},
582 address = {Washington, DC, USA},
583}
584%
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