source: anr/anr.bib @ 338

Last change on this file since 338 was 335, checked in by coach, 14 years ago

Mise à jour INRIA Rennes - 28 janv
File size: 38.1 KB
Line 
1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% MDS
3%Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe,
4%de Paoli Serge and Vaumorin Emmanuel
5@inproceedings{mds1,
6  author    = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin and All},
7  title     = {Industrial IP integration flows based on IP-XACT standards},
8  booktitle = {Proceedings of the conference on Design, automation and test in Europe},
9  series    = {DATE'08},
10  year      = {2008},
11  isbn      = {978-3-9810801-3-1},
12  location  = {Munich, Germany},
13  pages     = {32--37},
14  numpages  = {6},
15  url       = {http://doi.acm.org/10.1145/1403375.1403386},
16  doi       = {http://doi.acm.org/10.1145/1403375.1403386},
17  acmid     = {1403386},
18  publisher = {ACM},
19  address   = {New York, NY, USA},
20} 
21
22@misc{mds2,
23  author       = {E. Vaumorin, M. Palus, F. Clermidy and J. Martin},
24  title        = {SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform},
25  howpublished = {\url{http://www.design-reuse.com/articles/18613/ip-xact-esl-noc.html}},
26  year         = {2008},
27}
28
29@misc{socketflow,
30  author       = {L. Maillet-Contoz, R. Lucas and E. Vaumorin},
31  title        = {SocKET design flow and Application on industrial use cases},
32  howpublished = {\url{http://socket.imag.fr/Presentations-socket/Vendredi15/Presentation_flot.pdf}},
33  note         = {home site: \url{http://socket.imag.fr/}},
34  year         = {2010},
35}
36
37@misc{dandr,
38  author       = {Marc van Hintum, Paul Williams},
39  title        = {The Value of High Quality IP-XACT XML},
40  howpublished = {\url{http://www.design-reuse.com/articles/19895/ip-xact-xml.html}},
41  year         = {2010},
42}
43
44@techreport{rapport-ministere,
45 author      = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy},
46 title       = {Briques g\'en\'eriques du logiciel embarqu\'e},
47 year        = {2010},
48 institution = {Mininist\'ere de l'industrie},
49}
50
51%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
52%%%%% LIP6
53% HPC
54@InProceedings{hpc06a,
55  author    = {{M.B. Gokhale and al.}},
56  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
57  booktitle = {Systems and Algorithms, CSREA Press},
58  pages     = {11-20},
59  year      = {2006},
60}
61@MISC{hpc06b,
62  author =       {{D. Buell}},
63  title  =   {{Programming Reconfigurable Computers}},
64  booktitle = {Summer Institute},
65  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
66  year =         {2006},
67}
68@InProceedings{hpc07a,
69  author =       {{T. Van Court and al.}},
70  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
71  booktitle = {Computer, vol. 40, no. 3},
72  pages     = {50-57},
73  month     = {mars},
74  year =         {2007},
75}
76@misc{hpc08,
77  title        = {Mitrionics},
78  howpublished = {http://www.mitrionics.com/},
79  year         = {2009},
80}
81@misc{hpc09,
82  title        = {Gidel},
83  howpublished = {http://www.gidel.com/},
84  year         = {2009},
85}
86@misc{hpc10,
87  title        = {Convey Computer},
88  howpublished = {http://www.conveycomputers.com/},
89  year         = {2009},
90}
91@InProceedings{hpc11,
92  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
93  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
94  booktitle = {HPRCTA},
95  year =         {2008},
96}
97@InProceedings{hpc12,
98  author =       {{P. Lysaght and J. Dunlop}},
99  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
100  booktitle = {Field Programmable Logic and Applications, Oxford, England},
101  month     = {Sept},
102  year =         {1993},
103}
104
105
106% System design
107@misc{soclib,
108  title        = {Soclib},
109  howpublished = {http://www.soclib.fr/},
110  year         = {2009},
111}
112
113@misc{system-generateur-for-dsp,
114  title        = {{System Generator for DSP}},
115  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
116  year         = {2009},
117}
118
119@misc{spoc-builder,
120  title        = {{sopc builder support}},
121  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
122  year         = {2009},
123}
124
125@InProceedings{cosy,
126    author = { J.Y Brunel and A. San Giovanni-Vincentelli and R. Krees and W. Kruijtzer },
127    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
128    booktitle = { Technologies for the Information Society },
129    publisher = { IOS Press },
130    year      = {1998},
131    pages     = {709-716},
132}
133
134@InProceedings{disydent05,
135  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}},
136  title =        {{Platform-based design from parallel C specifications}},
137  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
138  pages     = {1811--1826},
139  month     = {December},
140  year =         {2005},
141}
142@inproceedings{dspin08,
143 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
144 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
145 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
146 year = {2008},
147 isbn = {978-0-7695-3098-7},
148 pages = {139--148},
149 publisher = {IEEE Computer Society},
150 address = {Washington, DC, USA},
151 }
152
153
154% HLS
155% http://mesl.ucsd.edu/spark/index.shtml
156@INBOOK{spark04,
157  author     = {S. Gupta and al.},
158  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
159  publisher  = {Springer},
160  year       = {2004},
161}
162
163
164@INBOOK{ugh08,
165  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
166  title     = {User Guided High Level Synthesis},
167  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
168  publisher = {Springer},
169  year      = {2008},
170  chapter   = {10},
171  pages     = {139-148},
172}
173  %editor    = { Philippe Coussy and Adam Moriawiec},
174
175@misc{pico,
176  title        = {{PICO}},
177  howpublished = {http://www.synfora.com/},
178  year         = {2009},
179}
180
181@misc{catapult-c,
182  title        = {{CATAPULT-C Mentor HLS tool}},
183  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
184  year         = {2009},
185}
186
187@misc{cynthetizer,
188  title        = {{Forte's CYNTHESIZER}},
189  howpublished = {http://www.forteds.com/},
190  year         = {2009},
191}
192
193@inproceedings{IP-XACT-08,
194 author = {Kruijtzer, Wido and van der Wolf, Pieter and de Kock, Erwin and Stuyt, Jan and Ecker, Wolfgang and Mayer, Albrecht and Hustin, Serge and Amerijckx, Christophe and de Paoli, Serge and Vaumorin, Emmanuel},
195 title = {Industrial IP integration flows based on IP-XACT standards},
196 booktitle = {Proceedings of the conference on Design, automation and test in Europe},
197 series = {DATE '08},
198 year = {2008},
199 isbn = {978-3-9810801-3-1},
200 location = {Munich, Germany},
201 pages = {32--37},
202 numpages = {6},
203 url = {http://doi.acm.org/10.1145/1403375.1403386},
204 doi = {http://doi.acm.org/10.1145/1403375.1403386},
205 acmid = {1403386},
206 publisher = {ACM},
207 address = {New York, NY, USA},
208}
209
210
211%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
212%%% UBS
213
214@INBOOK{IEEEDT,
215author = {Philippe Coussy and Andres Takach},
216title = {Special Issue on High-Level Synthesis},
217journal ={IEEE Design and Test of Computers},
218volume = {25},issn = {0740-7475},
219year = {2008},
220pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
221publisher = {IEEE Computer Society},
222address = {Los Alamitos, CA, USA},}
223
224
225@BOOK{HLSBOOK,
226  author    = {P. Coussy and A. Morawiec},
227  title = {High-Level Synthesis: From Algorithm to Digital Circuits},
228  publisher = {Springer},
229  year      = {2008},
230}
231
232@BOOK{CATRENE,
233  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
234  title = {European Roadmap for EDA},
235  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
236  year      = {2009},
237}
238
239@INBOOK{gaut08,
240  author    = {P. Coussy and al.},
241  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
242  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
243  publisher = {Springer},
244  year      = {2008},
245}
246
247@article{DBLP:journals/dt/CoussyT09,
248  author    = {Philippe Coussy and
249               Andres Takach},
250  title     = {Guest Editors' Introduction: Raising the Abstraction Level
251               of Hardware Design},
252  journal   = {IEEE Design {\&} Test of Computers},
253  volume    = {26},
254  number    = {4},
255  year      = {2009},
256  pages     = {4-6},
257  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
258  bibsource = {DBLP, http://dblp.uni-trier.de}
259}
260
261
262@article{DBLP:journals/dt/CoussyGMT09,
263  author    = {Philippe Coussy and
264               Daniel D. Gajski and
265               Michael Meredith and
266               Andres Takach},
267  title     = {An Introduction to High-Level Synthesis},
268  journal   = {IEEE Design {\&} Test of Computers},
269  volume    = {26},
270  number    = {4},
271  year      = {2009},
272  pages     = {8-17},
273  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
274  bibsource = {DBLP, http://dblp.uni-trier.de}
275}
276
277
278@article{DBLP:journals/vlsisp/ThabetCHM09,
279  author    = {Farhat Thabet and
280               Philippe Coussy and
281               Dominique Heller and
282               Eric Martin},
283  title     = {Exploration and Rapid Prototyping of DSP Applications using
284               SystemC Behavioral Simulation and High-level Synthesis},
285  journal   = {Signal Processing Systems},
286  volume    = {56},
287  number    = {2-3},
288  year      = {2009},
289  pages     = {167-186},
290  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
291  bibsource = {DBLP, http://dblp.uni-trier.de}
292}
293
294
295
296@inproceedings{CHAVET:2007:HAL-00153994:1,
297        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
298        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
299        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
300        language = {{A}nglais},
301        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
302        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
303        publisher = {{L}ibrary of {C}ongress },
304        pages = {2946 },
305        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
306        editor = {{IEEE} },
307        note = {{ISBN}:1-4244-0921-7 },
308        audience = {internationale },
309    day = {28},
310    month = {05},
311    year = {2007},
312    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
313    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
314}
315
316
317@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
318  author    = {Cyrille Chavet and
319               Caaliph Andriamisaina and
320               Philippe Coussy and
321               Emmanuel Casseau and
322               Emmanuel Juin and
323               Pascal Urard and
324               Eric Martin},
325  title     = {A design flow dedicated to multi-mode architectures for
326               DSP applications},
327  booktitle = {ICCAD},
328  year      = {2007},
329  pages     = {604-611},
330  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
331  crossref  = {DBLP:conf/iccad/2007},
332  bibsource = {DBLP, http://dblp.uni-trier.de}
333}
334
335
336@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
337  author    = {Cyrille Chavet and
338               Philippe Coussy and
339               Pascal Urard and
340               Eric Martin},
341  title     = {A design methodology for space-time adapter},
342  booktitle = {ACM Great Lakes Symposium on VLSI},
343  year      = {2007},
344  pages     = {347-352},
345  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
346  crossref  = {DBLP:conf/glvlsi/2007},
347  bibsource = {DBLP, http://dblp.uni-trier.de}
348}
349
350
351@inproceedings{CHAVET:2007:HAL-00154025:1,
352        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
353        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
354        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
355        language = {{A}nglais},
356        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
357        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
358        publisher = {{E}urasip },
359        pages = {??? },
360        address = {{P}oznan {P}ologne },
361        audience = {internationale },
362    day = {03},
363    month = {09},
364    year = {2007},
365    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
366    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
367}
368
369
370@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
371        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
372        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
373        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
374        language = {{A}nglais},
375        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
376        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
377        publisher = {{AHS} },
378        pages = {7 },
379        address = {{E}dinburgh {R}oyaume-{U}ni },
380        audience = {internationale },
381    year = {2007},
382    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
383    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
384}
385
386
387@inproceedings{COUSSY:2005:HAL-00077301:1,
388        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
389        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
390        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
391        keywords = {{DSP} application, synthesis under memory and communication constraints},
392        language = {{A}nglais},
393        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
394        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
395        publisher = {{IEEE} },
396        pages = {{V}ol. {V} p. 61-64 },
397        editor = {{IEEEE} },
398    year = {2005},
399    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
400    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
401}
402
403
404
405%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
406%%%%% IRISA
407@InProceedings{KluterCodes08,
408  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
409  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
410  booktitle = {ISSS/CODES},
411  year =         {2008},
412}
413
414@InProceedings{KluterDAC09,
415  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
416  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
417  booktitle = {Design Automation Conference (DAC)},
418  year =         {2009},
419}
420
421@InProceedings{YuCodes04,
422  author =       {{Pan Yu and Tulika Mitra}},
423  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
424  booktitle = {ISSS/CODES},
425  year =         {2004},
426}
427
428@InProceedings{Dinh08,
429  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
430  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
431  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
432  year =         {2008},
433}
434
435@Misc{NIOS2UG,
436  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
437  year =         {2008},
438}
439
440%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
441%%% CITI
442@book{Polis,
443  author = {Balarin, Felice},
444  publisher = {Kluwer Academic Publishers},
445  title = {Hardware-software co-design of embedded systems : the POLIS
446        approach},
447  year = {1997}
448}
449
450@INPROCEEDINGS{Coware,
451  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
452                Rompaey and Steven Vercauteren and Diederik Verkest},
453  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
454  booktitle = {Proceedings of the IEEE},
455  year = {1997},
456  pages = {391--418}
457}
458
459@article{Jantsch,
460  author = {Mattias O'Nil and Axel Jantsch},
461  title = {Device Driver and DMA Controller Synthesis from HW/SW
462                        Communication protocol specifications},
463  journal = {Design Automation for Embedded Systems},
464  year = {2001},
465  volume = {6},
466  pages = {177-205}
467}
468
469@InProceedings{Park01,
470  author =   {Joonseok Park and Pedro C.~Diniz},
471  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
472                Data Applications on {FPGA}-Based Computing Engines},
473  booktitle =    {International Symposium on System Synthesis (ISSS)},
474  pages = {221-226},
475  year =     {2001},
476}
477
478@article{FR-vlsi,
479  author = {Antoine Fraboulet and Tanguy Risset},
480  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
481  journal = {Journal of VLSI Signal Processing},
482  publisher = {Springer Science},
483  year = {2007},
484  volume = {59},
485  pages = {73-85}
486}
487
488@InProceedings{jerraya,
489  author =   {Sungjoo Yoo and Jerraya Ahmed},
490  title =    {Introduction to Hardware Abstraction Layers for SoC},
491  OPTcrossref =  {},
492  OPTkey =   {},
493  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
494  pages =    {336 -- 337},
495  year =     2003,
496  OPTeditor =    {},
497  OPTvolume =    {},
498  OPTnumber =    {},
499  OPTseries =    {},
500  OPTaddress =   {},
501  OPTmonth =     {},
502  OPTorganization = {},
503  OPTpublisher = {},
504  OPTnote =      {},
505  OPTannote =    {}
506}
507
508@INPROCEEDINGS{FAUST,
509  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
510        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
511        P. Penard and  A. Bouttier and  F. Berens}, 
512  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
513  pages = {},
514  BOOKTITLE="ISSCC\'2007", 
515  year = {2007},
516  publisher = {IEEE Computer Society},
517  address = {San Francisco, USA},
518};
519
520@inproceedings{JerrayaPetrot,
521 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
522 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
523 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
524 year = {2006},
525 isbn = {1-59593-381-6},
526 pages = {280--285},
527 location = {San Francisco, CA, USA},
528 publisher = {ACM},
529 address = {New York, NY, USA},
530}
531
532@inproceedings{mwmr,
533 author = {E. Faure and A. Greiner and D. Genius},
534 title = {A generic hardware/software communication mechanism for
535          Multi-Processor System on Chip, Targeting Telecommunication Applications},
536 booktitle = {ReCoSoC'06},
537 year = {2006},
538 pages = {237--242},
539 address = {Montpellier, France}
540 }
541
542@inproceedings{Alberto,
543  author    = {Roberto Passerone and
544               James A. Rowson and
545               Alberto L. Sangiovanni-Vincentelli},
546  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
547  booktitle = {DAC},
548  year      = {1998},
549  pages     = {8-13}
550}
551
552@article{Avnit,
553  author    = {Karin Avnit and
554               Vijay D'Silva and
555               Arcot Sowmya and
556               S. Ramesh and
557               Sri Parameswaran},
558  title     = {Provably correct on-chip communication: A formal approach
559               to automatic protocol converter synthesis},
560  journal   = {ACM Trans. Design Autom. Electr. Syst.},
561  volume    = {14},
562  number    = {2},
563  year      = {2009}
564}
565
566@inproceedings{smith,
567  author    = {James Smith and
568               Giovanni De Micheli},
569  title     = {Automated Composition of Hardware Components},
570  booktitle = {DAC},
571  year      = {1998},
572  pages     = {14-19}
573}
574
575@inproceedings{Narayan,
576  author    = {Sanjiv Narayan and
577               Daniel Gajski},
578  title     = {Interfacing Incompatible Protocols Using Interface Process
579               Generation},
580  booktitle = {DAC},
581  year      = {1995},
582  pages     = {468-473}
583}
584
585@TECHREPORT{Ptolemy,
586  AUTHOR       = { E.A. Lee et al.},
587  INSTITUTION  = {University of California, Berkeley},
588  NUMBER       = {UCB/ERL No. M99/37},
589  TITLE        = {Overview of the Ptolemy Project},
590  YEAR         = {1999},
591  MONTH        = {july}
592}
593
594@article{syntol,
595    author={Paul Feautrier},
596    title={Scalable and Structured Scheduling},
597    journal={Int. J. of Parallel Programming},
598    year=2006,
599    month=May, number=5, volume=34,
600    pages="459--487"
601}
602
603@InProceedings{bee,
604  author={Christophe Alias and Fabrice Baray and Alain Darte},
605  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
606  booktitle = {LCTES},
607  year = {2007},
608  publisher = {ACM}
609}
610
611%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
612
613@inproceedings{DAC09,
614 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
615 title = {Way Stealing: cache-assisted automatic instruction set extensions},
616 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
617 year = {2009},
618 isbn = {978-1-60558-497-3},
619 pages = {31--36},
620 location = {San Francisco, California},
621 doi = {http://doi.acm.org/10.1145/1629911.1629923},
622 publisher = {ACM},
623 address = {New York, NY, USA},
624 }
625
626@inproceedings{CODES08,
627 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
628 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
629 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
630 year = {2008},
631 isbn = {978-1-60558-470-6},
632 pages = {243--248},
633 location = {Atlanta, GA, USA},
634 doi = {http://doi.acm.org/10.1145/1450135.1450191},
635 publisher = {ACM},
636 address = {New York, NY, USA},
637 }
638 
639@article{TVLSI06,
640        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
641 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
642 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
643 volume = {14},
644 number = {9},
645 year = {2006},
646 issn = {1063-8210},
647 pages = {986--997},
648 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
649 publisher = {IEEE Educational Activities Department},
650 address = {Piscataway, NJ, USA},
651}
652
653
654@Book{NIOS2,
655  title =        {{Nios II Processor Reference Handbook}},
656  publisher =    {Altera},
657  year =         {2009},
658}
659
660
661@inproceedings{ARC08,
662 author = {Galuzzi, Carlo and Bertels, Koen},
663 title = {The Instruction-Set Extension Problem: A Survey},
664 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
665 year = {2008},
666 isbn = {978-3-540-78609-2},
667 pages = {209--220},
668 location = {London, UK},
669 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
670 publisher = {Springer-Verlag},
671 address = {Berlin, Heidelberg},
672 }
673
674@inproceedings{CODES99,
675 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
676 title = {{A flexible code generation framework for the design of application specific programmable processors}},
677 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
678 year = {1999},
679 pages = {27--31},
680 location = {Rome, Italy},
681 publisher = {ACM},
682 address = {New York, NY, USA},
683 }
684
685@inproceedings{ASAP05,
686 author = {L'Hours, Ludovic},
687 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
688 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
689 year = {2005},
690 pages = {127--133},
691 publisher = {IEEE Computer Society},
692 address = {Washington, DC, USA},
693}
694
695@inproceedings{roma,
696 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
697 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
698 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
699 year = {2009},
700 pages = {39--49},
701 location = {Karlsruhe, Germany},
702 publisher = {Springer-Verlag},
703 address = {Berlin, Heidelberg},
704 }
705
706%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
707
708@inproceedings{thales-viola,
709 author = {Viola, Jones},
710 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
711 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
712 year = {2001},
713}
714@INPROCEEDINGS{FP:96
715        ,AUTHOR = "Paul Feautrier"
716        ,TITLE = "Automatic Parallelization in the Polytope Model"
717        ,BOOKTITLE = "The Data-Parallel Programming Model"
718        ,YEAR = 1996   
719        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
720        ,PAGES = "79--103"
721        ,VOLUME = "LNCS 1132"
722        ,PUBLISHER = "Springer"
723}
724
725@book{DRV:2000,
726    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
727    title={Scheduling and automatic Parallelization},
728    publisher={Birkh\"auser}, year=2000
729}
730
731@Article{Feau:92aa,
732  author =       "Paul Feautrier",
733  title =        "Some Efficient Solutions to the Affine Scheduling
734                 Problem, {I}, One Dimensional Time",
735  volume =       "21",
736  number =       "5",
737  month =        Oct,
738  pages =        "313--348",
739  journal =      "Int. J. of Parallel Programming",
740  year =         "1992"
741}
742
743@Article{Feau:92bb,
744  author =       "Paul Feautrier",
745  title =        "Some Efficient Solutions to the Affine Scheduling
746                 Problem, {II}, Multidimensional Time",
747  volume =       "21",
748  number =       "6",
749  journal =      "Int. J. of Parallel Programming",
750  month =        Dec,
751  pages =        "389--420",
752  year =         "1992"
753}
754
755@ARTICLE{Feau:96
756        ,AUTHOR = {Paul Feautrier}
757        ,TITLE = {Distribution Automatique des Donn\'es et des
758         calculs} 
759        ,JOURNAL = {T.S.I.}
760        ,YEAR = 1996, VOLUME = 15, NUMBER = 5, PAGES = {529--557}
761}
762
763%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
764%%% IA
765
766@PHDTHESIS{ia-hdr-phd,
767  author    = {Ivan Aug\'{e}},
768  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
769               Synth\`ese de haut niveau \& Int\'egration
770               des syst\`emes mat\'eriel/logiciel},
771  school    = {Universit\'e Pierre et Marie Curie},
772  year      = {2009},
773  month     = {12},
774}
775
776@MISC{ia-hdr,
777  author    = {Ivan Aug\'{e}},
778  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
779               Synth\`ese de haut niveau \& Int\'egration
780               des syst\`emes mat\'eriel/logiciel},
781  howpublished = {Universit\'e Pierre et Marie Curie},
782  year      = {2009},
783  month     = {12},
784}
785
786@INBOOK{ia-ugh08,
787  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
788  title     = {User Guided High Level Synthesis},
789  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
790  publisher = {Springer},
791  chapter   = {10},
792  year      = {2008},
793  pages     = {139-148},
794}
795  %editor    = {Philippe Coussy and Adam Moriawiec},
796
797@misc{ia-ugh-09-aspdac,
798  author   = {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
799  title    = {User Guided High Level Synthesis},
800  booktitle= {Workshop "High-Level Synthesis: Next Step to Efficient ESL Design",
801                      in conjunction with ASP-DAC},
802  year     = {2009},
803}
804
805@misc{ia-ugh-08-date,
806  author =  {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
807  title = {User Guided High Level Synthesis},
808  booktitle= { Workshop "The New Wave of the High-Level Synthesis",
809                      in conjunction with DATE},
810  year       = {2008},
811}
812
813%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
814%%% AG
815
816@article{ag-1,
817    author = {Zhen Zhang and Alain Greiner and Mounir Benabdenbi},
818    title = {Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components},
819    journal ={On-Line Testing Symposium, IEEE International},
820    volume = {0},
821    isbn = {978-1-4244-7724-1},
822    year = {2010},
823    pages = {194-196},
824    doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560209},
825    publisher = {IEEE Computer Society},
826    address = {Los Alamitos, CA, USA},
827}
828
829@inproceedings{ag-2,
830    author    = {Greiner Alain and Faure Etienne and Pouillon Nicolas and Genius Dani\'ela},
831    title     = {A Generic Hardware/Software Communication Middleware for
832                 Streaming Applications on Shared Memory Multi Processor Systems-on-Chip},
833    booktitle = {Forum on Specification \& Design Languages (FDL 2009)},
834    isbn      = { 978-2-9530504-1-7},
835    month     = {September},
836    year      = {2009},
837    address   = {Nice, France},
838}
839
840@inproceedings{ag-3,
841    author    = {Porquet, Jo\"{e}l and Schwarz, Christian and Greiner, Alain},
842    title     = {Multi-compartment: A new architecture for secure
843                 co-hosting on SoC },
844    booktitle = {Proceedings of the 11th international conference on System-on-chip},
845    series    = {SOC'09},
846    month     = {October},
847    year      = {2009},
848    isbn      = {978-1-4244-4466-3},
849    location  = {Tampere, Finland},
850    pages     = {124-127},
851    numpages  = {4},
852    url       = {http://portal.acm.org/citation.cfm?id=1736530.1736555},
853    publisher = {IEEE Press},
854    address   = {Piscataway, NJ, USA},
855}
856
857@inproceedings{ag-4,
858    author    = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
859    title     = {Physical Implementation of the DSPIN Network-on-Chip in the
860                 FAUST Architecture},
861    booktitle = {Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
862    series    = {NOCS'08},
863    year      = {2008},
864    month     = {April},
865    isbn      = {978-0-7695-3098-7},
866    location  = {Newcastle, UK},
867    pages     = {139-148},
868    numpages = {10},
869    url = {http://portal.acm.org/citation.cfm?id=1397757.1397994},
870    publisher = {IEEE Computer Society},
871    address   = {Washington, DC, USA},
872}
873
874@inproceedings{mutek,
875        author = {Fr\'ed\'eric P\'etrot and Pascal Gomez},
876        title = {Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect},
877        booktitle = {Proceedings of the conference on Design, Automation and Test in Europe},
878        year = {2003},
879        isbn = {0-7695-1870-2-2},
880        pages = {20051},
881        publisher = {IEEE Computer Society},
882        address_hide = {Washington, DC, USA},
883}
884@inproceedings{dna,
885Author = {Xavier Gu\'erin and Fr\'ed\'eric P\'etrot},
886booktitle={IEEE International Conf. on Application -specific Systems, Architectures and Processors},
887Title = {A {S}ystem {F}ramework for the {D}esign of {E}mbedded {S}oftware {T}argeting {H}eterogeneous {M}ulti-{C}ore {S}o{C}s},
888Year = {2009},
889    pages     = {153-160},
890}
891
892%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
893%%% CA
894
895@InProceedings{ca:arc,
896  author =       {Christophe Alias and Bogdan Pasca and Alexandru Plesco},
897  title =        {Automatic Generation of FPGA-Specific Pipelined Accelerators},
898  booktitle =    {7th International Symposium on Applied Reconfigurable Computing (ARC)},
899  year =         {2011},
900  publisher =    {Springer LNCS}
901}
902
903@InProceedings{ca:chuba,
904  author =       {Christophe Alias and Alain Darte and Alexandru Plesco},
905  title =        {Optimizing {DDR-SDRAM} Communications at {C}-level for Automatically-Generated Hardware Accelerators. {A}n Experience With the {A}ltera {C2H HLS} Tool},
906  booktitle =    {IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
907  year =         {2010}
908}
909
910@InProceedings{ca:nuca,
911  author =       {Qingda Lu and Christophe Alias and Uday Bondhugula and Sriram Krishnamoorthy and J. Ramanujam and Atanas Rountev and P. Sadayappan and Yongjian Chen and Haibo Lin and Tin-fook Ngai},
912  title =        {Data Layout Transformation for Enhancing Locality on {NUCA} Chip Multiprocessors},
913  booktitle =    {ACM/IEEE Conference on Parallel Architectures and Compilation Techniques (PACT)},
914  year =         {2009}
915}
916
917
918%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
919%%% FC
920
921@InProceedings{    Martin09c,
922 author        = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.},
923 title          = {Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system},
924 address       = {Boston, MA, USA}, 
925month         = jul,
926 year           = 2009,
927booktitle ={Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors},
928pages = {145-152},
929publisher = {IEEE Computer Society},
930        x-proceedings = {yes}, 
931        x-international-audience = {yes}, 
932        x-editorial-board = {yes}, 
933        x-invited-conference = {no},
934        x-hal = {no}
935}
936
937@InProceedings{Martin09d,
938 author        = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.},
939 title          = {Constraint-Driven Identification of Application Specific Instructions in the DURASE system},
940 booktitle     = {Proc. of Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
941 address = {Samos, Greece},
942month         = jul,
943 year           = 2009,
944volume = {5657},
945series = {Lecture Notes in Computer Science},
946pages = {194-203},
947publisher = {Springer},
948        x-proceedings = {yes}, 
949        x-international-audience = {yes}, 
950        x-editorial-board = {yes}, 
951        x-invited-conference = {no}, 
952        x-hal = {no}
953}
954@InProceedings{    Wolinski09a,
955 author        = {Wolinski, Ch. and Kuchcinski, K. and Raffin, E. and Charot, F.},
956 title          = {Architecture-Driven Synthesis of Reconfigurable Cells},
957booktitle = {{Proc. of the 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD)}},
958 address       = {Patras, Greece}, 
959month         = sep,
960 year           = 2009,
961pages = {531 - 538 },
962doi={10.1109/DSD.2009.183},
963        x-proceedings = {yes}, 
964        x-international-audience = {yes}, 
965        x-editorial-board = {yes}, 
966        x-invited-conference = {no}, 
967        x-hal = {no}
968}
969@inproceedings{RAFFIN:2010:INRIA-00539874:1,
970    HAL_ID = {inria-00539874},
971    URL = {http://hal.inria.fr/inria-00539874/en/},
972    title = { {S}cheduling, {B}inding and {R}outing {S}ystem for a {R}un-{T}ime {R}econfigurable {O}perator {B}ased {M}ultimedia {A}rchitecture},
973    author = {{R}affin, {E}rwan and {W}olinski, {C}hristophe and {C}harot, {F}ran{\c{c}}ois and {K}uchcinski, {K}rzysztof and {G}uyetant, {S}t{\'e}phane and {C}hevobbe, {S}t{\'e}phane and {C}asseau, {E}mmanuel},
974    booktitle = {Conference on {D}esign and {A}rchitectures for {S}ignal and {I}mage {P}rocessing ({DASIP} 2010)},
975    address = {{E}dinburgh {R}oyaume-{U}ni },
976    audience = {internationale },
977    month = oct,
978    year = {2010},
979    URL = {http://hal.inria.fr/inria-00539874/PDF/dasip2010.pdf},
980    x-hal={inria-00539874},
981}
Note: See TracBrowser for help on using the repository browser.