source: anr/coach_global.txt @ 357

Last change on this file since 357 was 273, checked in by alain, 15 years ago
File size: 8.1 KB
Line 
1
2The market of digital systems is about 4,600 M\$ today and is estimated to
35,600 M\$ in 2012. However the ever growing applications complexity involves
4integration of heterogeneous technologies and requires the design of
5complex Multi-Processors System on Chip (MPSoC).
6
7During the last decade, the design of ASICs (Application Specific
8Integrated Circuits) appeared to be more and more reserved to high volume markets, because
9the design and fabrication costs of such components exploded, due to increasing NRE (Non
10Recurring-Engineering) costs.
11Fortunately, FPGA (Field Programmable Gate Array) components, such as the
12Virtex5 family from Xilinx or the Stratix4 family from Altera, can nowadays
13implement a complete MPSoC with multiple processors and several dedicated
14coprocessors for a few Keuros per device. Many applications are initially captured
15algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
16in tools that can provide an implementation path directly from HLLs to hardware.
17Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
18Co-design, High-Level Synthesis...) are now mature and allow the automation of
19a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
20on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
21However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
22methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
23designs written in C/C++ language and implementing the function straight into FPGA.
24We believe that coupling FPGA technologies and ESL methodologies
25will allow both SMEs (Small and Medium Enterprise) and
26major companies to design innovative devices and to enter new, low and
27medium volume markets.
28
29The objective of COACH is to provide an integrated design flow, based on the
30SoCLib infrastructure~\cite{soclib}, and optimized for the design of
31multi-processors digital systems targeting FPGA devices.
32Such digital systems are generally integrated
33into one or several chips, and there are two types of applications:
34They can be embedded (autonomous) applications
35such as personal digital assistants (PDA), ambiant computing components,
36or wireless sensor networks (WSN).
37They can also be extension boards connected to a PC to accelerate a specific computation,
38as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
39
40The COACH environment will integrate several hardware and software technologies:
41
42Design Space Exploration:
43    The COACH environment will allow to describe an application as a process
44        network i.e. a set of tasks communicating through FIFO channels.
45        COACH will allow to map the application on a shared-memory, MPSoC architecture.
46    It will permit to easily explore the design space to help the system designer
47        to define the proper hardware/software partitioning of the application.
48    For each point in the design space, metrics such as throughput, latency, power
49    consumption, silicon area, memory allocation and data locality will be provided.
50    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
51    and high-level estimation methodologies.
52       
53Hardware Accelerators Synthesis (HAS):
54    COACH will allow the automatic generation of hardware accelerators when required.
55    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
56    (ASIP) design environment and source-level transformation tools (loop transformations
57    and memory optimisation) will be provided.
58    This will allow further exploration of the micro-architectural design space.
59    HLS tools are sensitive to the coding style of the input specification and the domain
60    they target (control vs. data dominated).
61    The HLS tools of COACH will support a common language and coding style to avoid
62    re-engineering by the designer.
63
64Platform based design:
65    COACH will handle both Altera and Xilinx FPGA devices.
66    COACH will define architectural templates that can be customized by adding
67    dedicated coprocessors and ASIPs and by fixing template parameters such as
68    the number of embedded processors, the number of sizes of embedded memory banks
69    or the embedded the operating system.
70    However, the specification of the application will be independant of both the
71    architectural template and the target FPGA device.
72    Basically, the following three architectural templates will be provided:
73    - A Neutral architectural template based on the SoCLib IP core library and the
74      VCI/OCP communication infrastructure.
75    - An Altera architectural template based on the Altera IP core library, the
76      AVALON system bus and the NIOS processor.
77    - A Xilinx architectural template based on the Xilinx IP core library, the PLB
78      system bus and the Microblaze processor.
79
80Hardware/Software communication middleware:
81    COACH will implement an homogeneous HW/SW communication infrastructure and
82    communication APIs (Application Programming Interface), that will be used for
83    communications between software tasks running on embedded processors and
84    dedicated hardware coprocessors.
85
86The COACH design flow will be dedicated to system designers, and will as
87much as possible hide the hardware characteristics to the end-user.
88
89To reach this ambitious goal, the project will rely on the experience and the
90complementariness of partners in the following domains:
91Operating system and communication middleware (Tima, Lip6),
92MPSoC architectures (Tima, Lab-Sticc, Lip6),
93ASIP architectures (Inria/Cairn),
94High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip).
95
96The COACH project does not start from scratch.
97It stronly relies on the SoCLib virtual prototyping platform for prototyping,
98(DSX, component library), operating systems (MUTEKH, DNA/OS).
99It also leverages on  several existing technologies:
100on the GAUT and UGH tools for HLS,
101on the ROMA project for ASIP,
102on the SYNTOL and BEE tools for source-level analysis and transformations
103and on the Xilinx and Altera IP core libraries.
104Finally it will use the Xilinx and Altera logic and physical synthesis
105tools to generate the FPGA configuration bitstreams.
106
107The COACH proposal has been prepared during one year by a technical working group
108involving the 5 academic partners (one monthly meeting from january 2009 to february
1092010). The objective was to analyse the issues of integrating
110and enhancing the existing tools and tecnnologies into a unique framework.
111Most of the general software architecture of the proposed design flow (including the
112exchange format specification) has been define by this working group.
113Because the COACH project leanes on the ANR SoCLib platform, it may be described as an
114extension of the SoCLib platform.
115
116Two major FPGA companies are involved in the project: Xilinx will contribute
117as a contractual partner providing documentation and manpower; Altera will contribute as
118a supporter, providing documentation and development boards. These two companies are strongly motivated
119to help the COACH project to generate efficient bitsreams for both FPGA families.
120The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
121real use cases to benchmark the COACH design environment and to analyze the designer productivity
122improvements.
123
124Following the general policy of the SoCLib platform, the COACH project will be an open
125infrastructure, available in the framework of the SoCLib server.
126The architectural templates, and the COACH software tools will be distributed under the
127GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
128IP core library) will be freely available for non commercial use. For industrial exploitation
129the technology providers are ready to propose commercial licenses, directly to the end user,
130or through a third party.
131
132Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the
133"letters of interest", that have collected during the preparation of the project :
134- ADACSYS
135- MDS
136- INPIXAL
137- CAMKA System
138- ATEME
139- ALSIM
140- SILICOMP-AQL
141- ABOUND Logic
142- EADS-ASTRIUM
Note: See TracBrowser for help on using the repository browser.