source: anr/coach_summary.txt @ 270

The objective of COACH is to provide an integrated design flow, based on the
SoCLib virtual prototyping infrastructure, and optimized for the design of
multi-processors digital systems targeting FPGA devices.
Such digital systems are generally integrated
into one or several chips, and there are two types of applications:
They can be embedded (autonomous) applications
such as personal digital assistants (PDA), ambiant computing components,
or wireless sensor networks (WSN).
They can also be extension boards connected to a PC to accelerate a specific computation,
as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).

The COACH project will provide three hardware architectural templates:

    - A Neutral architectural template based on the SoCLib IP core library and the
      VCI/OCP communication infrastructure.
    - An Altera architectural template based on the Altera IP core library, the
      AVALON system bus and the NIOS processor.
    - A Xilinx architectural template based on the Xilinx IP core library, the PLB
      system bus and the Microblaze processor.

The COACH design flow will be dedicated to system designers, and will as
much as possible hide the hardware characteristics to the end-user.
The specification of the application will be independant from the
architectural template and the target FPGA device.

To reach this ambitious goal, the project will rely on the experience and the
complementariness of partners in the following domains:
- Operating system and communication middleware (Tima, Lip6),
- MPSoC architectures (Tima, Lab-Sticc, Lip6),
- ASIP architectures (Inria/Cairn),
- High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip).

The COACH project does not start from scratch.
It stronly relies on the SoCLib virtual prototyping platform for prototyping, 
(DSX, component library), operating systems (MUTEKH, DNA/OS).
It also leverages on  several existing technologies: the GAUT and UGH tools for HLS, 
the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations
and on the Xilinx and Altera IP core libraries.
Finally it will use the Xilinx and Altera logic and physical synthesis 
tools to generate the FPGA configuration bitstreams.

Two major FPGA companies are involved in the project: Xilinx will contribute
as a contractual partner providing documentation and manpower; Altera will contribute as
a supporter, providing documentation and development boards. These two companies are strongly motivated
to help the COACH project to generate efficient bitsreams for both FPGA families.
The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide
real use cases to benchmark the COACH design environment and to analyze the designer productivity 
improvements. 

Following the general policy of the SoCLib platform, the COACH project will be an open
infrastructure, available in the framework of the SoCLib server.
The architectural templates, and the COACH software tools will be distributed under the
GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
IP core library) will be freely available for non commercial use. For industrial exploitation
the technology providers are ready to propose commercial licenses, directly to the end user,
or through a third party.

Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the 
"letters of interest", that have collected during the preparation of the project :
- ADACSYS 
- MDS 
- INPIXAL 
- CAMKA System 
- ATEME 
- ALSIM
- SILICOMP-AQL
- ABOUND Logic 
- EADS-ASTRIUM