1 | The objective of COACH is to provide an integrated design flow, based on the |
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2 | SoCLib virtual prototyping infrastructure, and optimized for the design of |
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3 | multi-processors digital systems targeting FPGA devices. |
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4 | Such digital systems are generally integrated |
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5 | into one or several chips, and there are two types of applications: |
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6 | They can be embedded (autonomous) applications |
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7 | such as personal digital assistants (PDA), ambiant computing components, |
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8 | or wireless sensor networks (WSN). |
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9 | They can also be extension boards connected to a PC to accelerate a specific computation, |
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10 | as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). |
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11 | |
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12 | The COACH project will provide three hardware architectural templates: |
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13 | |
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14 | - A Neutral architectural template based on the SoCLib IP core library and the |
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15 | VCI/OCP communication infrastructure. |
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16 | - An Altera architectural template based on the Altera IP core library, the |
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17 | AVALON system bus and the NIOS processor. |
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18 | - A Xilinx architectural template based on the Xilinx IP core library, the PLB |
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19 | system bus and the Microblaze processor. |
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20 | |
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21 | The COACH design flow will be dedicated to system designers, and will as |
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22 | much as possible hide the hardware characteristics to the end-user. |
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23 | The specification of the application will be independant from the |
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24 | architectural template and the target FPGA device. |
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25 | |
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26 | To reach this ambitious goal, the project will rely on the experience and the |
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27 | complementariness of partners in the following domains: |
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28 | - Operating system and communication middleware (Tima, Lip6), |
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29 | - MPSoC architectures (Tima, Lab-Sticc, Lip6), |
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30 | - ASIP architectures (Inria/Cairn), |
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31 | - High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip). |
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32 | |
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33 | The COACH project does not start from scratch. |
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34 | It stronly relies on the SoCLib virtual prototyping platform for prototyping, |
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35 | (DSX, component library), operating systems (MUTEKH, DNA/OS). |
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36 | It also leverages on several existing technologies: the GAUT and UGH tools for HLS, |
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37 | the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations |
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38 | and on the Xilinx and Altera IP core libraries. |
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39 | Finally it will use the Xilinx and Altera logic and physical synthesis |
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40 | tools to generate the FPGA configuration bitstreams. |
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41 | |
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42 | Two major FPGA companies are involved in the project: Xilinx will contribute |
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43 | as a contractual partner providing documentation and manpower; Altera will contribute as |
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44 | a supporter, providing documentation and development boards. These two companies are strongly motivated |
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45 | to help the COACH project to generate efficient bitsreams for both FPGA families. |
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46 | The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide |
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47 | real use cases to benchmark the COACH design environment and to analyze the designer productivity |
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48 | improvements. |
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49 | |
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50 | Following the general policy of the SoCLib platform, the COACH project will be an open |
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51 | infrastructure, available in the framework of the SoCLib server. |
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52 | The architectural templates, and the COACH software tools will be distributed under the |
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53 | GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib |
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54 | IP core library) will be freely available for non commercial use. For industrial exploitation |
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55 | the technology providers are ready to propose commercial licenses, directly to the end user, |
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56 | or through a third party. |
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57 | |
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58 | Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the |
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59 | "letters of interest", that have collected during the preparation of the project : |
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60 | - ADACSYS |
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61 | - MDS |
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62 | - INPIXAL |
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63 | - CAMKA System |
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64 | - ATEME |
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65 | - ALSIM |
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66 | - SILICOMP-AQL |
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67 | - ABOUND Logic |
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68 | - EADS-ASTRIUM |
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