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[273] | 1 | |
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| 2 | |
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| 3 | The project is split into 8 tasks described in short below: |
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| 4 | |
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| 5 | T1) Project management |
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| 6 | |
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| 7 | This task relates to the monitoring of the COACH project. It includes a monthy meeting of the steering committee. |
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| 8 | |
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| 9 | T2) Backbone |
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| 10 | |
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| 11 | This task tackles the fundamental points of the project that are the defintion of the COACH inputs and outputs, the inter-tools exchange formats, the three supported architectural templates, the hardware/software communication middleware, and the general design flow. This task contains also the development of the associated tools. |
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| 12 | |
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| 13 | T3) System generation |
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| 14 | |
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| 15 | This task addresses the virtual prototyping and the generation of the final bitstream (including hardware and |
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| 16 | embedded software). |
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| 17 | |
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| 18 | T4) Hardware accelerator synthesis front-end |
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| 19 | |
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| 20 | This task mainly focusses on four functionalities: optimization of the memory usage, parallelism enhancement through loop transformations, coarse grain parallelization and ASIP generation. |
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| 21 | |
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| 22 | T5) Hardware accelerator synthesis back-end |
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| 23 | |
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| 24 | This task groups two functionalities: High-Level Synthesis of data dominated coprocessors and High Level Synthesis of control dominated coprocessors. It contains also the development of a a generic retiming mechanism |
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| 25 | to adapt the coprocessors to the system frequency. |
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| 26 | |
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| 27 | T6) PC/FPGA communication middleware |
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| 28 | |
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| 29 | This task is mainly dedicated to HPC. Subtasks are mainly the partitioning evaluation tool, the software drivers for both PC and FPGA-SoC sides, the hardware communication components and the support for dynamic partial reconfiguration. |
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| 30 | |
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| 31 | T7) Industrial demonstrators |
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| 32 | |
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| 33 | This task groups the demonstrators of the COACH project. Most subtasks are industrial applications that will be used to evaluate the COACH framework. Another subtask is to evaluate the interfacing between the COACH framework and a proprietary system-level design tool (Thales). A third subtask is to evaluate the COACH framework on a third embedded FPGA architecture (Flexras). |
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| 34 | |
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| 35 | T8) Dissemination |
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| 36 | |
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| 37 | This task is related to the dissemination of the project results. It mainly consists of the production of the 4 COACH releases and the publication on the WEB server, the production of tutorials and user manuals, the publication of research papers in international journals and conferences and the organization of workshops and tutorials in international conferences. |
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| 38 | |
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