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source: anr/flow.fig @ 246

Last change on this file since 246 was 226, checked in by coach, 15 years ago
UBS
File size: 6.6 KB

Rev	Line
[226]	1	#FIG 3.2 Produced by xfig version 3.2.5b
[1]	2	Landscape
	3	Center
	4	Inches
	5	Letter
	6	100.00
	7	Single
	8	-2
	9	1200 2
	10	5 1 1 1 0 7 50 -1 -1 4.000 0 0 1 0 10197.794 13038.971 5400 2700 6750 2175 10650 1650
	11	1 1 1.00 60.00 120.00
	12	5 1 1 1 0 7 50 -1 -1 4.000 0 0 1 0 10745.564 6247.984 8250 4050 9750 3075 10875 2925
	13	1 1 1.00 60.00 120.00
	14	5 1 1 1 0 7 50 -1 -1 4.000 0 1 1 0 9862.500 2550.000 9375 4275 10350 4275 10950 3975
	15	1 1 1.00 60.00 120.00
	16	5 1 1 1 0 7 50 -1 -1 4.000 0 1 1 0 9315.226 707.707 8775 5100 10575 4950 12300 3975
	17	1 1 1.00 60.00 120.00
	18	5 1 0 2 0 7 50 -1 -1 0.000 0 1 1 0 8562.500 4437.500 8850 4950 9075 4725 9150 4425
	19	1 1 2.00 60.00 120.00
	20	6 4275 2475 6675 4950
	21	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	22	6450 3375 4500 3375 4500 2700 6450 2700 6450 3375
	23	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	24	6450 4725 4500 4725 4500 4050 6450 4050 6450 4725
	25	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
	26	1 1 3.00 60.00 120.00
	27	1 1 3.00 60.00 120.00
	28	5475 3375 5475 4050
	29	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	30	6600 4875 4350 4875 4350 2550 6600 2550 6600 4875
[226]	31	4 0 0 50 -1 2 16 0.0000 4 255 1815 4650 3075 Application PC\001
	32	4 0 0 50 -1 2 16 0.0000 4 255 1950 4575 4425 Application SoC\001
[1]	33	-6
	34	6 1725 3300 3375 4275
	35	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	36	3300 4200 1800 4200 1800 3375 3300 3375 3300 4200
[226]	37	4 0 0 50 -1 2 16 0.0000 4 195 585 2325 3750 HPC\001
	38	4 0 0 50 -1 2 16 0.0000 4 255 1335 1950 4050 application\001
[1]	39	-6
	40	6 7500 975 9750 3675
	41	6 7725 1125 9525 3225
	42	6 7725 1125 8175 2775
	43	6 7800 1275 8100 2175
[226]	44	4 1 0 50 -1 2 16 0.0000 4 195 165 7950 1500 P\001
	45	4 1 0 50 -1 2 16 0.0000 4 195 195 7950 1725 R\001
	46	4 1 0 50 -1 2 16 0.0000 4 195 225 7950 1950 O\001
	47	4 1 0 50 -1 2 16 0.0000 4 195 195 7949 2175 C\001
[1]	48	-6
	49	2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
	50	7800 1200 8100 1200 8100 2700 7800 2700 7800 1200
	51	-6
	52	6 8175 1125 8625 2775
	53	6 8250 1275 8550 1950
[226]	54	4 1 0 50 -1 2 16 0.0000 4 195 195 8400 1500 R\001
	55	4 1 0 50 -1 2 16 0.0000 4 195 195 8400 1725 A\001
	56	4 1 0 50 -1 2 16 0.0000 4 195 255 8400 1950 M\001
[1]	57	-6
	58	2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
	59	8250 1200 8550 1200 8550 2700 8250 2700 8250 1200
	60	-6
	61	6 8625 1125 9075 2775
	62	2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
	63	8700 1200 9000 1200 9000 2700 8700 2700 8700 1200
[226]	64	4 1 0 50 -1 2 16 0.0000 4 195 105 8850 1500 I\001
	65	4 1 0 50 -1 2 16 0.0000 4 195 225 8850 1725 O\001
[1]	66	-6
	67	6 7725 2775 9525 3225
	68	2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	69	7800 2850 9450 2850 9450 3150 7800 3150 7800 2850
[226]	70	4 1 0 50 -1 2 16 0.0000 4 195 540 8625 3075 BUS\001
[1]	71	-6
	72	-6
	73	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	74	9675 3600 9675 1050 7575 1050 7575 3600 9675 3600
	75	2 1 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 2
	76	7575 3300 9675 3300
[226]	77	4 1 0 50 -1 2 16 0.0000 4 195 1080 8625 3525 Platform\001
[1]	78	-6
	79	6 10575 2250 12825 4950
	80	6 10800 2400 12600 4500
	81	6 10800 2400 11250 4050
	82	6 10875 2550 11175 3450
[226]	83	4 1 0 50 -1 2 16 0.0000 4 195 165 11025 2775 P\001
	84	4 1 0 50 -1 2 16 0.0000 4 195 195 11025 3000 R\001
	85	4 1 0 50 -1 2 16 0.0000 4 195 225 11025 3225 O\001
	86	4 1 0 50 -1 2 16 0.0000 4 195 195 11024 3450 C\001
[1]	87	-6
	88	2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
	89	10875 2475 11175 2475 11175 3975 10875 3975 10875 2475
	90	-6
	91	6 11250 2400 11700 4050
	92	6 11325 2550 11625 3225
[226]	93	4 1 0 50 -1 2 16 0.0000 4 195 195 11475 2775 R\001
	94	4 1 0 50 -1 2 16 0.0000 4 195 195 11475 3000 A\001
	95	4 1 0 50 -1 2 16 0.0000 4 195 255 11475 3225 M\001
[1]	96	-6
	97	2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
	98	11325 2475 11625 2475 11625 3975 11325 3975 11325 2475
	99	-6
	100	6 11700 2400 12150 4050
	101	2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
	102	11775 2475 12075 2475 12075 3975 11775 3975 11775 2475
[226]	103	4 1 0 50 -1 2 16 0.0000 4 195 105 11925 2775 I\001
	104	4 1 0 50 -1 2 16 0.0000 4 195 225 11925 3000 O\001
[1]	105	-6
	106	6 12150 2400 12600 4050
	107	6 12225 2475 12525 3825
[226]	108	4 1 0 50 -1 2 16 0.0000 4 195 165 12375 3150 P\001
	109	4 1 0 50 -1 2 16 0.0000 4 195 195 12375 3375 R\001
	110	4 1 0 50 -1 2 16 0.0000 4 195 225 12375 3600 O\001
	111	4 1 0 50 -1 2 16 0.0000 4 195 195 12374 3825 C\001
	112	4 1 0 50 -1 2 16 0.0000 4 195 225 12375 2925 O\001
	113	4 1 0 50 -1 2 16 0.0000 4 195 195 12375 2700 C\001
[1]	114	-6
	115	2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
	116	12225 2475 12525 2475 12525 3975 12225 3975 12225 2475
	117	-6
	118	6 10800 4050 12600 4500
	119	2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	120	10875 4125 12525 4125 12525 4425 10875 4425 10875 4125
[226]	121	4 1 0 50 -1 2 16 0.0000 4 195 540 11700 4350 BUS\001
[1]	122	-6
	123	-6
	124	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	125	12750 4875 12750 2325 10650 2325 10650 4875 12750 4875
	126	2 1 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 2
	127	10650 4575 12750 4575
[226]	128	4 1 0 50 -1 2 16 0.0000 4 195 1080 11700 4800 Platform\001
[1]	129	-6
	130	6 11100 300 12375 900
[226]	131	4 0 0 50 -1 2 16 0.0000 4 255 1395 11100 525 Application\001
	132	4 0 0 50 -1 2 16 0.0000 4 255 1425 11100 825 compilation\001
[1]	133	-6
[226]	134	6 1725 4650 3375 5625
	135	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	136	3300 5550 1800 5550 1800 4725 3300 4725 3300 5550
	137	4 0 0 50 -1 2 16 0.0000 4 195 1245 2025 5100 Embedded\001
	138	4 0 0 50 -1 2 16 0.0000 4 255 1335 1950 5400 application\001
	139	-6
	140	1 4 0 2 0 7 50 -1 -1 0.000 1 0.0000 8595 5027 228 228 8367 5027 8823 5027
	141	1 4 0 2 0 7 50 -1 -1 0.000 1 0.0000 8103 4200 228 228 7875 4200 8331 4200
	142	1 4 0 2 0 7 50 -1 -1 0.000 1 0.0000 9118 4213 228 228 8890 4213 9346 4213
[1]	143	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	144	1 1 2.00 60.00 120.00
	145	6600 4425 7650 4425
	146	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	147	1 1 2.00 60.00 120.00
	148	3300 3750 4350 3750
	149	2 1 1 2 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	150	7050 150 7050 6450
	151	2 1 1 2 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	152	10125 150 10125 6450
	153	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
	154	1 1 2.00 60.00 120.00
	155	5475 6450 5475 4875
	156	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
	157	1 1 2.00 60.00 120.00
	158	11700 6450 11700 4875
	159	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	160	12750 1950 10650 1950 10650 1275 12750 1275 12750 1950
	161	2 1 1 2 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	162	3750 150 3750 6450
[226]	163	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	164	1 1 2.00 60.00 120.00
	165	3300 5175 7650 5175
	166	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
	167	1 1 2.00 60.00 120.00
	168	8925 4200 8325 4200
	169	2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
	170	1 1 2.00 60.00 120.00
	171	8550 6450 8550 5775
	172	2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
	173	9600 5775 7650 5775 7650 3900 9600 3900 9600 5775
	174	2 1 1 2 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
	175	7650 5325 9600 5325
	176	4 0 0 50 -1 2 16 0.0000 4 195 1305 11100 1650 Executable\001
	177	4 0 0 50 -1 2 16 0.0000 4 255 1065 11250 6750 Running\001
	178	4 0 0 50 -1 2 16 0.0000 4 255 690 2250 675 Input\001
	179	4 0 0 50 -1 2 16 0.0000 4 255 1290 4800 675 HPC setup\001
	180	4 0 0 50 -1 2 16 0.0000 4 255 1305 8025 675 SoC design\001
	181	4 0 0 50 -1 2 12 0.0000 4 150 240 8475 5100 T0\001
	182	4 0 0 50 -1 2 12 0.0000 4 150 240 8025 4275 T1\001
	183	4 0 0 50 -1 2 12 0.0000 4 150 240 9000 4275 T2\001
	184	4 0 0 50 -1 2 16 0.0000 4 195 1905 7725 5625 Process network\001
	185	4 0 0 50 -1 2 16 0.0000 4 255 2535 4200 6750 Performance analysis\001
	186	4 0 0 50 -1 2 16 0.0000 4 255 2535 7350 6750 Performance analysis\001

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