source: anr/obsolete/coach_irisa.bib @ 18

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1@InProceedings{KluterCodes08,
2  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
3  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
4  booktitle = {ISSS/CODES},
5  year =         {2008},
6}
7
8@InProceedings{KluterDAC09,
9  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
10  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
11  booktitle = {Design Automation Conference (DAC)},
12  year =         {2009},
13}
14
15@InProceedings{YuCodes04,
16  author =       {{Pan Yu and Tulika Mitra}},
17  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
18  booktitle = {ISSS/CODES},
19  year =         {2004},
20}
21
22@InProceedings{Dinh08,
23  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
24  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
25  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
26  year =         {2008},
27}
28
29@Misc{NIOS2UG,
30  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
31  year =         {2008},
32 
33}
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