[16] | 1 | % les objectifs globaux, |
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| 2 | An embedded system is an application integrated into one or several chips |
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| 3 | in order to accelerate it or to embedd it into a small device such as a |
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| 4 | personal digital assistant (PDA). This topic is investigated since 80s |
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| 5 | using Applications Specific Integrated Circuits (ASIC), Digital Signal |
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| 6 | Processing (DSP) and parallel computing on multiprocessor machines or |
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| 7 | networks. More recently, since end of 90s, other technologies appeared |
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| 8 | like Very Large Instruction Word (VLIW), Application Specific Instruction |
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| 9 | Processors (ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC). |
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| 10 | \\ |
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| 11 | During these last decades embedded system was reserved to major industrial |
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| 12 | companies targeting high volume market due to the design and fabrication |
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| 13 | costs. |
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| 14 | Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx |
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| 15 | and Stratix4 from Altera, can implement a SoC with multiple processors and |
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| 16 | several coprocessors for less than 10K euros per item. |
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| 17 | In addition, High Level Synthesis (HLS) becomes more mature and allows to |
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| 18 | automate design and to drastically decrease its cost in terms of man power. |
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| 19 | Thus, both FPGA and HLS tend to spread over HPC for small companies |
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| 20 | targeting low volume markets. |
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| 21 | \par |
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| 22 | To get an efficient embedded system, designer has to take into account |
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| 23 | application characteristics when it chooses one of the former technologies. |
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| 24 | This choice is not easy and in most cases designer has to try different |
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| 25 | technologies to retain the most adapted one. |
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| 26 | \\ |
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| 27 | The first objective of COACH is to provide a framework to |
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| 28 | design embedded system on FPGA device. |
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| 29 | COACH framework allows designer to explore various software/hardware |
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| 30 | partitions of the target application, to run timing and functional |
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| 31 | simulations and to generate automatically both the software and the |
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| 32 | synthesizable description of the hardware. |
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| 33 | The main topics of the project are: |
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| 34 | \begin{itemize} |
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| 35 | \item Design space exploration: It consists in analysing the application |
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| 36 | runnig on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and |
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| 37 | hardware/software partitioning of tasks depending on technology choice. |
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| 38 | This exploration is driven basically by throughput, latency and power |
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| 39 | consumption criteria. |
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| 40 | \item Micro-architectural exploration: When hardware components are |
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| 41 | required, the HLS tools of the framework generate them automatically. At |
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| 42 | this stage the framework provides various HLS tools allowing the |
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| 43 | micro-architectural space design exploration. The exploration criteria are |
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| 44 | also throughput, latency and power consumption. |
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| 45 | % FIXME |
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| 46 | %CA At this stage, preliminary source-level transformations will be |
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| 47 | %CA required to improve the efficiency of the target component. |
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| 48 | %CA COACH will also provide such facilities, such as automatic parallelization |
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| 49 | %CA and memory optimisation. |
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| 50 | \item Performance measurement: For each point of design space exploration, |
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| 51 | metrics of criteria are available such as throughput, latency, power |
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| 52 | consumption, area, memory allocation and data locality. |
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| 53 | They are evaluated using virtual prototyping, estimation or analysing |
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| 54 | methodologies. |
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| 55 | \item Targeted hardware technology: The COACH description of system is |
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| 56 | independent of the FPGA family. |
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| 57 | Every point of the design exploration space can be implemented on any FPGA |
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| 58 | having the required resources. |
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| 59 | Basically, COACH handles both Altera and Xilinx FPGA families and supports |
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| 60 | 3 generic target architectures: |
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| 61 | the COACH architecture based on the MIPS of the TSAR ANR project and a VCI ring bus, |
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| 62 | the Altera architecture based on the NIOS and AVALON bus, |
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| 63 | the Xilinx architecture based on the MICROBLAZE and OPB bus. |
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| 64 | \end{itemize} |
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| 65 | As an extension of embedded system design, COACH deals also with High |
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| 66 | Performance Computing (HPC). |
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| 67 | In HPC, the kind of targeted application is an existing one running on PC. |
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| 68 | COACH helps designer to accelerate it by migrating critical parts into a |
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| 69 | SoC implemented on a FPGA plugged to the PC bus.\\ |
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| 70 | Finally COACH will be developped under the General Public Licence for the software, |
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| 71 | and USAGE LIBRE NON COMMERCIAL for the COACH architecture. |
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| 72 | % |
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| 73 | % verrous scientifiques et techniques |
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| 74 | \mbox{}\vspace*{.9ex}\par |
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| 75 | System design is a very complicated task and in this project we try to simplify it |
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| 76 | as much as possible. For this purpose we have to deal with the following scientific |
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| 77 | and technological barriers. |
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| 78 | \begin{itemize} |
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| 79 | \item The run frequency of the coprocessors generated by the HLS must respect |
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| 80 | accurately the system frequency given bt the processors and bus. |
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| 81 | \item HLS tools are sensitive to the style in which the algorithm is written |
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| 82 | and the domain they target. The HLS tools of COACH must have a common language |
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| 83 | and style to avoid engineering work to the designer. |
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| 84 | \item The main problem in HPC is in the communication between the PC and the SoC |
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| 85 | firstly at the efficiency level and secondly to eliminate enginnering effort to |
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| 86 | implement it. |
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| 87 | \end{itemize} |
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| 88 | % |
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| 89 | % le programme de travail |
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| 90 | \vspace*{.9ex}\par |
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| 91 | COACH is the result of the will of several laboratories to unify their know |
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| 92 | hows and skills in the following domains: Operating system and hardware |
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| 93 | communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and |
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| 94 | HLS (LIP6, Lab-STIC and LIP). |
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| 95 | So COACH does not starts from scratch but it relies |
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| 96 | on SocLib~\cite{soclib} with the MUTEX and DNA/OS operating system for |
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| 97 | system prototyping, |
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| 98 | on BEE~\cite{bee}, GAUT~\cite{gaut08}, ROMA~\cite{roma}, SYNTOL~\cite{syntol} |
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| 99 | and UGH~\cite{ugh08} for HLS. |
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| 100 | The project objective is to integrate and enhance these various tools into |
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| 101 | a unique free framework masking as much as possible these domains and its |
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| 102 | different tools to the system designer. The main steps of this projects are: |
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| 103 | 1) Definition of the designer input as set of communicating tasks, each |
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| 104 | task beeing described in C++ language. |
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| 105 | 2) Definition of the xhls format, an internal format for representing a |
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| 106 | task. |
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| 107 | 3) Developping a GCC addon for generating the xhls date from a C++ task |
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| 108 | description. |
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| 109 | 4) Adapting the existing HLS tools to read and write xhls format and |
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| 110 | enhancing them. This allows to swap from one tool to the other and |
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| 111 | chain them. |
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| 112 | 5) Modifying the Design System Explorator of SocLib to let the designer |
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| 113 | to explore the design space and then to generate the bitstream to |
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| 114 | the target FPGA. |
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| 115 | \par |
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| 116 | The role of the industrials BUL, THALES, XXX, XXX is to provide real |
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| 117 | benchmark to guide the design of framework and prove that COACH is |
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| 118 | usuable and cover a large spectrum of applications. |
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| 119 | % |
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| 120 | % les retombées scientifiques, techniques et économiques |
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| 121 | \vspace*{.9ex}\par |
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| 122 | The main scientific contributions of the project are |
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| 123 | firstly to make high level synthesis an elementary tool of system design, |
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| 124 | seconly to unify various synthesis techniques (same input and output formats) |
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| 125 | allowing the designer to swap from one to an other and even to chain them |
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| 126 | without rewritting effort, |
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| 127 | and finally to provide a system description independent of the target |
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| 128 | architecture and the FPGA family. |
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| 129 | \par |
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| 130 | The market of embedded system and HPC is about 4,600 M\$ today and is |
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| 131 | estimated to 5,600 M\$ in 2012. |
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| 132 | This market is dominated by Multi-core CPUs based solution and is controlled |
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| 133 | by major companies that can support the very high Non Recurring Engineering (NRE) |
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| 134 | costs involved in designing such system. |
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| 135 | Small companies can only be present in this market with GPUs based solutions that have |
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| 136 | low NRE costs but limit the application domains.\\ |
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| 137 | COACH reduces the NRE costs to the design costs (the FPGA device being only a few |
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| 138 | K\euro) and reduces drastically them. |
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| 139 | So one can expect that tools targeting FPGA and dedicated to software developpers |
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| 140 | will gain market share over Multi-core CPUs and GPUs HPC based solutions. |
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| 141 | Moreover this market can also be boosted by small and even very small new companies |
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| 142 | that will be able to propose embedded system and accelerating solutions for standard |
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| 143 | software applications with acceptable prices.\\ |
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| 144 | The two major FPGA companies Altera and Xilinx expect thus by supporting |
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| 145 | and participating in this project. |
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| 146 | |
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