source: anr/section-1.tex @ 117

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1% les objectifs globaux,
2The market of digital systems is about 4,600 M\$ today and is estimated to
35,600 M\$ in 2012. However the ever growing applications complexity involves
4integration of heterogeneous technologies and requires the design of
5complex Multi-Processors System on Chip (MPSoC).
6\\
7During the last decade, the design of ASICs (Application Specific
8Integrated Circuits) appeared to be more and more reserved to high volume markets, because
9the design and fabrication costs of such components exploded, due to increasing NRE (Non
10Recurring-Engineering) costs.
11Fortunately, FPGA (Field Programmable Gate Array) components, such as the
12Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
13implement a complete MPSoC with multiple processors and several dedicated
14coprocessors for a few keuros per device.
15In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
16Co-design, High-Level Synthesis...) are now mature and allow the automation of
17a system level design flow that targets FPGA devices.
18We believe that coupling FPGA technologies and ESL methodologies
19will allow both SMEs (Small and Medium Enterprise) and
20major companies to design innovative devices and to enter new, low and
21medium volume markets.
22\parlf
23The objective of COACH is to provide an integrated design flow, based on the
24SoCLib infrastructure~\cite{soclib}, and optimized for the design of
25multi-processors digital systems targeting FPGA devices.
26Such digital systems are generally integrated
27into one or several chips, and there are two types of applications:
28They can be embedded (autonomous) applications
29such as personal digital assistants (PDA), ambiant computing components,
30or wireless sensor networks (WSN)
31They can also be extension boards connected to a PC to accelerate a specific computation,
32as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
33\parlf
34%verrous scientifiques et techniques
35The COACH environment will integrate several hardware and software technologies:
36\begin{description}
37\item[Design Space Exploration:]
38    The COACH environment will support design space exploration to help the
39    system designer to select and parameterize the target architecture, and to
40    define the proper hardware/software partitioning of the application.
41    For each point in the design space, metrics such as throughput, latency, power
42    consumption, silicon area, memory allocation and data locality will be provided.
43    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
44    and high-level estimation methodologies.
45\item[Hardware Accelerators Synthesis (HAS):]
46    COACH will allow the automatic generation of hardware accelerators when required.
47    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
48    (ASIP) design environment and source-level transformation tools (loop transformations
49    and memory optimisation) will be provided.
50    This will allow further exploration of the micro-architectural design space.
51    HLS tools are sensitive to the coding style of the input specification and the domain
52    they target (control vs. data dominated).
53    The HLS tools of COACH will support a common language and coding style to avoid
54    re-engineering by the designer.
55\item[Platform based design:] 
56    COACH will handle both \altera and \xilinx FPGA devices.
57    COACH will define architectural templates that can be customized by adding
58    dedicated coprocessors and ASIPs and by fixing template parameters such as
59    the number of embedded processors or the number of sizes of embedde memory banks,
60    or the embedded the operating system.
61    Basically, the 3 following architectural templates will be provided:
62    \begin{enumerate}
63    \item A Neutral architectural template based on the SoCLib IP core library and the
64      VCI/OCP communication infrastructure.
65    \item An \altera architectural template based on the \altera IP core library and the
66      AVALON system bus.
67    \item A \xilinx architectural template based on the Xlinx IP core library and the PLB
68      system bus.
69    \end{enumerate}
70    Moreover, the specification of the application will be independant of both the
71    architectural template and the target FPGA device.
72\item[Hardware/Software communication middleware:]
73    Coach will implement an homogeneous HW/SW communication infrastructure and
74    communication APIs (Application Programming Interface), that will be used for
75    communications between software tasks running on embedded processors and
76    dedicated hardware coprocessors,
77\end{description}
78The COACH design flow will be dedicated to system designers, and will as
79much as possible hide the hardware characteristics to the end user.
80%From the end user point of view, the specification of the application will be
81%independant from both the architectural template and from the selected FPGA
82%family.
83\parlf
84% le programme de travail
85%The COACH project targets fundamental issues related to design methodologies for
86%digital systems by providing estimation, exploration and design tools targeting both
87%performance and power optimization at all the abstraction levels of the flow (system,
88%architecture, algorithm and logic).
89To reach this ambitious goal, the project will rely on the experience and the
90complementariness of partners in the following domains:
91Operating system and communication middleware (\tima, \upmc),
92MPSoC architectures (\tima, \ubs, \upmc),
93ASIP architectures (\irisa),
94High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip).
95\\
96The COACH project does not start from scratch.
97It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
98
99\mustbecompleted{FIXME == SUPPRIMER LE H de Mutek ???}
100(DSX, component library), operating systems (MutekH, DNA/OS).
101It also leverages on  several existing technologies:
102on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
103on the ROMA~\cite{roma} project for ASIP,
104on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
105and on the \xilinx and \altera IP core libraries.
106Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
107bitstreams.
108\parlf
109The COACH proposal has been prepared during one year by a technical working group
110involving the 5 academic partners (one monthly meeting from january 2009 to february
1112010). The objective was to analyse the issues of integrating
112and enhancing the existing tools and tecnnologies into a unique framework.
113Most of the general software architecture of the proposed design flow (including the
114exchange format specification) has been define by this working group.
115Because the SocLib platform is the base of this project, it may be described as an
116extension of the SoCLib platform.
117%The main development steps of the COACH project are:
118%\begin{enumerate}
119%   \item Definition of the end user inputs:
120%    The coarse grain parallelism of the application will be described as a communicating
121%    task graph, each task being described in C language.
122%    Similarly the architectural templates with their parameters and the design constraints
123%    will be specified.
124%  \item Definition of an internal format for representing task.
125%  \item Development of the GCC pluggin for generating the internal format of a
126%    C task.
127%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
128%    the internal format. This will allow to swap from one tool to another one, and to
129%    chain them if necessary.
130%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
131%    platform to generate the bitstream for the various FPGA families and architectural
132%    templates.
133%  \item Development of new tools such as ASIP compiler, HPC design environment and
134%    dynamic reconfiguration of FPGA devices.
135%\end{enumerate}
136\parlf
137Two major FPGA companies are involved in the project : \xilinx will contribute
138as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
139providing documentation and development boards. These two companies are strongly motivated
140to help the COACH project to generate efficient bitsream for both FPGA families.
141The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
142real use cases to benchmark the COACH design environment.
143\parlf
144Following the general policy of the SoCLib platform, the COACH project will be an open
145infrastructure, available in the framework of the SoCLib server.
146The architectural templates, and the COACH software tools will be distributed under the
147GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
148IP core library) will be freely available for non commercial use. For industrial exploitation
149the technology providers are ready to propose commercial licenses, directly to the end user,
150or through a third party.
151
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