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1% les objectifs globaux,
2An embedded system is an application integrated into one or several chips
3in order to accelerate it or to embedd it into a small device such as a
4personal digital assistant (PDA). This topic is investigated since 80s
5using Applications Specific Integrated Circuits (ASIC), Digital Signal
6Processing (DSP) and parallel computing on multiprocessor machines or
7networks.  More recently, since end of 90s, other technologies appeared
8like Very Large Instruction Word (VLIW), Application Specific Instruction
9Processors (ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC).
10\\
11During these last decades embedded system was reserved to major industrial
12companies targeting high volume market due to the design and fabrication
13costs.
14Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
15and Stratix4 from Altera, can implement a SoC with multiple processors and
16several coprocessors for less than 10K euros per item.
17In addition, High Level Synthesis (HLS) becomes more mature and allows to
18automate design and to drastically decrease its cost in terms of man power.
19Thus, both FPGA and HLS tend to spread over HPC for small companies
20targeting low volume markets.
21\par
22To get an efficient embedded system, designer has to take into account
23application characteristics when it chooses one of the former technologies.
24This choice is not easy and in most cases designer has to try different
25technologies to retain the most adapted one.
26\\
27The first objective of COACH is to provide a framework to
28design embedded system on FPGA device.
29COACH framework allows designer to explore various software/hardware
30partitions of the target application, to run timing and functional
31simulations and to generate automatically both the software and the
32synthesizable description of the hardware.
33The main topics of the project are:
34\begin{itemize} 
35\item Design space exploration: It consists in analysing the application
36runnig on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
37hardware/software partitioning of tasks depending on technology choice.
38This exploration is driven basically by throughput, latency and power
39consumption criteria.
40\item Micro-architectural exploration: When hardware components are
41required, the HLS tools of the framework generate them automatically. At
42this stage the framework provides various HLS tools allowing the
43micro-architectural space design exploration. The exploration criteria are
44also throughput, latency and power consumption.
45% FIXME
46%CA At this stage, preliminary source-level transformations will be
47%CA required to improve the efficiency of the target component.
48%CA COACH will also provide such facilities, such as automatic parallelization
49%CA and memory optimisation.
50\item Performance measurement: For each point of design space exploration,
51metrics of criteria are available such as throughput, latency, power
52consumption, area, memory allocation and data locality.
53They are evaluated using virtual prototyping, estimation or analysing
54methodologies.
55\item Targeted hardware technology: The COACH description of system is
56independent of the FPGA family.
57Every point of the design exploration space can be implemented on any FPGA
58having the required resources.
59Basically, COACH handles both Altera and Xilinx FPGA families and supports
603 generic target architectures:
61the COACH architecture based on the MIPS of the TSAR ANR project and a VCI ring bus,
62the Altera architecture based on the NIOS and AVALON bus,
63the Xilinx architecture based on the MICROBLAZE and OPB bus.
64\end{itemize}
65As an extension of embedded system design, COACH deals also with High
66Performance Computing (HPC).
67In HPC, the kind of targeted application is an existing one running on PC.
68COACH helps designer to accelerate it by migrating critical parts into a
69SoC implemented on a FPGA plugged to the PC bus.\\
70Finally COACH will be developped under the General Public Licence for the software,
71and USAGE LIBRE NON COMMERCIAL for the COACH architecture.
72%
73% verrous scientifiques et techniques
74\mbox{}\vspace*{.9ex}\par
75System design is a very complicated task and in this project we try to simplify it
76as much as possible. For this purpose we have to deal with the following scientific
77and technological barriers.
78\begin{itemize}
79\item The run frequency of the coprocessors generated by the HLS must respect
80accurately the system frequency given bt the processors and bus.
81\item HLS tools are sensitive to the style in which the algorithm is written
82and the domain they target. The HLS tools of COACH must have a common language
83and style to avoid engineering work to the designer.
84\item The main problem in HPC is in the communication between the PC and the SoC
85firstly at the efficiency level and secondly to eliminate enginnering effort to
86implement it.
87\end{itemize}
88%
89% le programme de travail
90\vspace*{.9ex}\par
91COACH is the result of the will of several laboratories to unify their know
92hows and skills in the following domains: Operating system and hardware
93communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
94HLS (LIP6, Lab-STIC and LIP).
95So COACH does not starts from scratch but it relies
96on SocLib~\cite{soclib} with the MUTEX and DNA/OS operating system for
97system prototyping,
98on BEE~\cite{bee}, GAUT~\cite{gaut08}, ROMA~\cite{roma}, SYNTOL~\cite{syntol}
99and UGH~\cite{ugh08} for HLS.
100The project objective is to integrate and enhance these various tools into
101a unique free framework masking as much as possible these domains and its
102different tools to the system designer.  The main steps of this projects are:
1031) Definition of the designer input as set of communicating tasks, each
104task beeing described in C++ language.
1052) Definition of the xhls format, an internal format for representing a
106task.
1073) Developping a GCC addon for generating the xhls date from a C++ task
108description.
1094) Adapting the existing HLS tools to read and write xhls format and
110enhancing them. This allows to swap from one tool to the other and
111chain them.
1125) Modifying the Design System Explorator of SocLib to let the designer
113to explore the design space and then to generate the bitstream to
114the target FPGA.
115\par
116The role of the industrials BUL, THALES, XXX, XXX is to provide real
117benchmark to guide the design of framework and prove that COACH is
118usuable and cover a large spectrum of applications.
119%
120% les retombées scientifiques, techniques et économiques
121\vspace*{.9ex}\par
122The main scientific contributions of the project are
123firstly to make high level synthesis an elementary tool of system design,
124seconly to unify various synthesis techniques (same input and output formats)
125allowing the designer to swap from one to an other and even to chain them
126without rewritting effort,
127and finally to provide a system description independent of the target
128architecture and the FPGA family.
129\par
130The market of embedded system and HPC is about 4,600 M\$ today and is
131estimated to 5,600 M\$ in 2012.
132This market is dominated by Multi-core CPUs based solution and is controlled
133by major companies that can support the very high Non Recurring Engineering (NRE)
134costs involved in designing such system.
135Small companies can only be present in this market with GPUs based solutions that have
136low NRE costs but limit the application domains.\\
137COACH reduces the NRE costs to the design costs (the FPGA device being only a few
138K\euro) and reduces drastically them.
139So one can expect that tools targeting FPGA and dedicated to software developpers
140will gain market share over Multi-core CPUs and GPUs HPC based solutions.
141Moreover this market can also be boosted by small and even very small new companies
142that will be able to propose embedded system and accelerating solutions for standard
143software applications with acceptable prices.\\
144The two major FPGA companies Altera and Xilinx expect thus by supporting
145and participating in this project.
146
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