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1% les objectifs globaux,
2A digital system is an application integrated into one or several chips.
3These chips can be embedded in devices such as a personal digital assistant
4(PDA), ambiant computing component, wireless sensor network (WSN). They can
5also be used on a board connected to a PC to accelerate an application like
6in High-Performance Computing (HPC) and in High-Speed Signal Processing (HSSP).
7Digital system design has  been investigated since eighties by using Applications
8Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on
9multiprocessor machines or networks.  More recently, since the end of nineties,
10other technologies appeared like Very Large Instruction Word (VLIW), Application
11Specific Instruction Processors (ASIP), System on Chip (SoC), Multi-Processors
12SoC (MPSoC).
13\\
14During these last decades, digital systems are more and more reserved
15to major companies targeting high volume market due to the design and fabrication
16costs of ASIC technologies due to increasing NRE (Non Recurring-Engineering) charges.
17Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
18and Stratix4 from Altera, can implement a complete SoC with multiple processors and
19several coprocessors for less than 10K euros per device.
20In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
21Co-design, High-Level Synthesis...) become mature and allow to
22automate design and to drastically decrease its cost in terms of man power.
23Thus, coupling both FPGA and ESL methodologies will soon allow small and medium
24enterprises (SMEs) to get into new and low-volume markets, to design highly innovative devices,
25to prototype complete complex embedded systems, to realize HPC or HSSP applications.
26\par
27The objective of COACH is to provide an environment to design emmbedded systems and
28HPC applications on FPGA devices. The COACH framework will allow designer to explore various
29software/hardware partitioning scenario of the target application through timing and functional
30simulations and to generate automatically both the software and the
31synthesizable description of the hardware. Exploration and design are mainly
32driven by throughput, latency and/or power consumption criteria.
33The main contributions of the project are:
34\begin{itemize} 
35\item Targeted hardware architecture and technology:
36COACH will handle both Altera and Xilinx FPGA technologies. COACH will define
37architectural templates that can be customized by additional dedicated coprocessors and ASIPs.
38The parameters of the architectural templates will be the number of CPU, the operating  system... 
39%the coprocessors, the number and the size of the FIFO communication channels
40Basically, the 3 following architectural templates will be provided:
41A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
42An Altera architectural template based on the NIOS and the AVALON bus,
43%FIXME
44% The following point has to be confirmed by XILINX
45% Microblaze+OPB => ARM+Amba ???
46A Xilinx architectural template based on the MICROBLAZE and the OPB bus.
47Moreover, the specification of the application will be independant of both the template
48architecture and the selected technology.
49\item Design space exploration: The COACH environment will allow to select and parametrize
50the target architecture, to define hardware/software partitioning and to profile the application.
51For each point of design space exploration, metrics such as throughput, latency, power consumption,
52area, memory allocation and data locality will be provided.
53This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
54\item Hardware accelerators synthesis (HAS): COACH will allow to generate automatically hardware accelerators
55when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and
56source-level transformations (loop transformations and memory optimisation) will be provided.
57This will allow to further explore the micro-architectural design space.
58\end{itemize}
59%In HPC, the kind of targeted application is an existing one running on PC.
60%COACH helps designer to accelerate it by migrating critical parts into a
61%SoC implemented on a FPGA plugged to the PC bus.\\
62%FIXME licence a speficier
63The COACH environment will be designed to abstract the hardware as much as possible to the end user.
64It will thus be mainly dedicated to system designers.
65Finally COACH will be developped under the General Public Licence for the software tools.
66and USAGE LIBRE NON COMMERCIAL for the COACH arhitecture.
67%The COACH architectural templates will be freely distributed.
68%
69% verrous scientifiques et techniques
70\mbox{}\vspace*{.9ex}\par
71System design is a very complex task this project will simplify as much as possible.
72For this purpose the following scientific and technological barriers will be addressed:
73\begin{itemize}
74\item The clock frequency of the coprocessors generated by the HLS must respect
75the frequency of the processors and the system bus.
76\item HLS tools are sensitive to the coding style of the input specification
77and the domain they target (control vs. data dominated). The HLS tools of COACH must have a
78common language and coding style to avoid engineering work to the designer.
79\item The main problem in HPC comes from timing performance and implementation of the communication
80between the PC and the FPGA.
81%FIXME: a completer loop tranfrom?, ASIP?, ...
82\end{itemize}
83%
84% le programme de travail
85\vspace*{.9ex}\par
86COACH is the result of the will of several laboratories to unify their know
87hows and skills in the following domains: Operating system and hardware
88communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
89HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
90COACH does not start from scratch but relies
91on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for
92SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on
93ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
94The project objective is to enhance and seamlessly integrate these tools into
95a unique open source framework.
96%masking these domains and its different tools to the system designer.
97The main steps of this project are:
981) Definition of the user inputs: application description as set of communicating tasks, each
99task beeing described in C++ language; architectural template with its parameters; design constraints.
1002) Definition of the internal \xcoach format for representing a task.
1013) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
1024) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to
103swap from one tool to an other one and to chain them.
1045) Modification of the Design System eXplorator DSX of the SocLib platform to let the user
105explore the design space and then to generate the bitstream.
106%FIXME : a completer
107\par
108The role of the industrial partners BULL, THALES, XXX is to provide real
109benchmarks to guide the design of the framework and to prove that COACH is
110usuable and cover a large spectrum of applications.
111%
112% les retombées scientifiques, techniques et économiques
113\vspace*{.9ex}\par
114The main scientific contributions of the project are:
115to make high-level synthesis an elementary tool of system design,
116to unify various synthesis techniques (same input and output formats)
117allowing the designer to swap from one to an other and even to chain them
118without rewritting effort,
119to provide a system description independent of the target architecture and
120the FPGA family.
121\par
122The market of embedded system and HPC is about 4,600 M\$ today and is
123estimated to 5,600 M\$ in 2012.
124This market is dominated by Multi-core CPUs based solution and is controlled
125by major companies that can support the very high Non Recurring Engineering (NRE)
126costs involved in designing such system.
127Small and medium companies can only be present in this market with GPUs based solutions that have
128low NRE costs but limit the application domains.\\
129COACH reduces the NRE costs to the design costs (the FPGA device being only a few
130K\euro) and reduces drastically them.
131So one can expect that tools targeting FPGA and dedicated to software developpers
132will gain market share over Multi-core CPUs and GPUs HPC based solutions.
133Moreover this market can also be boosted by small and even very small new companies
134that will be able to propose embedded system and accelerating solutions for standard
135software applications with acceptable prices.\\
136The two major FPGA companies Altera and Xilinx expect this by supporting
137and participating in this project.
138
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