source: anr/section-1.tex @ 248

Last change on this file since 248 was 246, checked in by coach, 15 years ago

UBS

File size: 9.7 KB
Line 
1% les objectifs globaux,
2The market of digital systems is about 4,600 M\$ today and is estimated to
35,600 M\$ in 2012. However the ever growing applications complexity involves
4integration of heterogeneous technologies and requires the design of
5complex Multi-Processors System on Chip (MPSoC).
6\\
7During the last decade, the design of ASICs (Application Specific
8Integrated Circuits) appeared to be more and more reserved to high volume markets, because
9the design and fabrication costs of such components exploded, due to increasing NRE (Non
10Recurring-Engineering) costs.
11Fortunately, FPGA (Field Programmable Gate Array) components, such as the
12Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
13implement a complete MPSoC with multiple processors and several dedicated
14coprocessors for a few Keuros per device. Many applications are initially captured
15algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
16in tools that can provide an implementation path directly from HLLs to hardware.
17Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
18Co-design, High-Level Synthesis...) are now mature and allow the automation of
19a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
20on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
21However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
22methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
23designs written in C/C++ language and implementing the function straight into FPGA.
24We believe that coupling FPGA technologies and ESL methodologies
25will allow both SMEs (Small and Medium Enterprise) and
26major companies to design innovative devices and to enter new, low and
27medium volume markets.
28\parlf
29The objective of COACH is to provide an integrated design flow, based on the
30SoCLib infrastructure~\cite{soclib}, and optimized for the design of
31multi-processors digital systems targeting FPGA devices.
32Such digital systems are generally integrated
33into one or several chips, and there are two types of applications:
34They can be embedded (autonomous) applications
35such as personal digital assistants (PDA), ambiant computing components,
36or wireless sensor networks (WSN).
37They can also be extension boards connected to a PC to accelerate a specific computation,
38as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
39\parlf
40%verrous scientifiques et techniques
41The COACH environment will integrate several hardware and software technologies:
42\begin{description}
43\item[Design Space Exploration:]
44    The COACH environment will support design space exploration to help the
45    system designer to select and parameterize the target architecture, and to
46    define the proper hardware/software partitioning of the application.
47    For each point in the design space, metrics such as throughput, latency, power
48    consumption, silicon area, memory allocation and data locality will be provided.
49    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
50    and high-level estimation methodologies.
51        \mustbecompleted{FIXME :: Question que l'on peut se poser sur DSE : quelle est la nouveaté la dedans ?
52        Doit on parler ici de modele de programmation, de mapping... qui permettent un DSE?}
53       
54\item[Hardware Accelerators Synthesis (HAS):]
55    COACH will allow the automatic generation of hardware accelerators when required.
56    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
57    (ASIP) design environment and source-level transformation tools (loop transformations
58    and memory optimisation) will be provided.
59    This will allow further exploration of the micro-architectural design space.
60    HLS tools are sensitive to the coding style of the input specification and the domain
61    they target (control vs. data dominated).
62    The HLS tools of COACH will support a common language and coding style to avoid
63    re-engineering by the designer.
64\item[Platform based design:] 
65    COACH will handle both \altera and \xilinx FPGA devices.
66    COACH will define architectural templates that can be customized by adding
67    dedicated coprocessors and ASIPs and by fixing template parameters such as
68    the number of embedded processors, the number of sizes of embedded memory banks
69    or the embedded the operating system.
70    However, the specification of the application will be independant of both the
71    architectural template and the target FPGA device.
72    Basically, the following three architectural templates will be provided:
73    \begin{enumerate}
74    \item A Neutral architectural template based on the SoCLib IP core library and the
75      VCI/OCP communication infrastructure.
76    \item An \altera architectural template based on the \altera IP core library, the
77      AVALON system bus and the NIOS processor.
78    \item A \xilinx architectural template based on the Xilinx IP core library, the PLB
79      system bus and the Microblaze processor.
80    \end{enumerate}
81\item[Hardware/Software communication middleware:]
82    COACH will implement an homogeneous HW/SW communication infrastructure and
83    communication APIs (Application Programming Interface), that will be used for
84    communications between software tasks running on embedded processors and
85    dedicated hardware coprocessors.
86\end{description}
87The COACH design flow will be dedicated to system designers, and will as
88much as possible hide the hardware characteristics to the end-user.
89%From the end user point of view, the specification of the application will be
90%independant from both the architectural template and from the selected FPGA
91%family.
92\parlf
93% le programme de travail
94%The COACH project targets fundamental issues related to design methodologies for
95%digital systems by providing estimation, exploration and design tools targeting both
96%performance and power optimization at all the abstraction levels of the flow (system,
97%architecture, algorithm and logic).
98To reach this ambitious goal, the project will rely on the experience and the
99complementariness of partners in the following domains:
100Operating system and communication middleware (\tima, \upmc),
101MPSoC architectures (\tima, \ubs, \upmc),
102ASIP architectures (\irisa),
103High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip).
104\\
105The COACH project does not start from scratch.
106It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS).
107It also leverages on  several existing technologies:
108on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
109on the ROMA~\cite{roma} project for ASIP,
110on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
111and on the \xilinx and \altera IP core libraries.
112Finally it will use the \xilinx and \altera logic and physical synthesis tools to generate the FPGA configuration
113bitstreams.
114\parlf
115The COACH proposal has been prepared during one year by a technical working group
116involving the 5 academic partners (one monthly meeting from january 2009 to february
1172010). The objective was to analyse the issues of integrating
118and enhancing the existing tools and tecnnologies into a unique framework.
119Most of the general software architecture of the proposed design flow (including the
120exchange format specification) has been define by this working group.
121Because the COACH project leanes on the ANR SoCLib platform, it may be described as an
122extension of the SoCLib platform.
123%The main development steps of the COACH project are:
124%\begin{enumerate}
125%   \item Definition of the end user inputs:
126%    The coarse grain parallelism of the application will be described as a communicating
127%    task graph, each task being described in C language.
128%    Similarly the architectural templates with their parameters and the design constraints
129%    will be specified.
130%  \item Definition of an internal format for representing task.
131%  \item Development of the GCC pluggin for generating the internal format of a
132%    C task.
133%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
134%    the internal format. This will allow to swap from one tool to another one, and to
135%    chain them if necessary.
136%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
137%    platform to generate the bitstream for the various FPGA families and architectural
138%    templates.
139%  \item Development of new tools such as ASIP compiler, HPC design environment and
140%    dynamic reconfiguration of FPGA devices.
141%\end{enumerate}
142\parlf
143Two major FPGA companies are involved in the project : \xilinx will contribute
144as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
145providing documentation and development boards. These two companies are strongly motivated
146to help the COACH project to generate efficient bitsreams for both FPGA families.
147The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
148real use cases to benchmark the COACH design environment and to analyze the designer productivity
149improvements.
150\parlf
151Following the general policy of the SoCLib platform, the COACH project will be an open
152infrastructure, available in the framework of the SoCLib server.
153The architectural templates, and the COACH software tools will be distributed under the
154GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
155IP core library) will be freely available for non commercial use. For industrial exploitation
156the technology providers are ready to propose commercial licenses, directly to the end user,
157or through a third party.
158
Note: See TracBrowser for help on using the repository browser.