% les objectifs globaux, 
The market of digital systems is about 4,600 M\$ today and is estimated to
5,600 M\$ in 2012. However the ever growing applications complexity involves
higher integration of heterogeneous technologies and requires the design of
complex Multi-Processors System on Chip (MPSoC).
During the last decade, the design of complex digital ASICs (Application Specific
Integrated Circuits) appeared to be more and more reserved to high volume markets, because
the design and fabrication costs of such components exploded, due to increasing NRE (Non
Recurring-Engineering) costs.
\\
FPGA (Field Programmable Gate Array) components, such as the
Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
implement a complete MPSoC with multiple processors and several
coprocessors for a few keuros per device.
In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
Co-design, High-Level Synthesis...) are now mature and allow the automation of
a system level design flow that targets FPGA devices.
We believe that coupling FPGA technologies and ESL methodologies
will allow both SMEs (Small and Medium Enterprise) and
major companies to design innovative devices and to enter new, low and
medium volume markets.
\\
The objective of COACH is to provide an integrated design flow, based on the
SoCLib infrastructure~\cite{soclib}, and optimized for the design of
multi-processors digital systems targetting FPGA devices.
Such digital systems are generally integrated
into one or several chips, and there are two types of applications:
It can be embedded (autonomous) applications
such as personal digital assistants (PDA), ambiant computing components
or wireless sensor networks (WSN)
They can also be extension boards connected to a PC to accelerate a specific computation,
as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
\\
The COACH project fundamental issues are related to design methodologies
for digital systems, providing estimation, exploration and design tools
targeting both performance and power optimization at all the abstraction
levels of the flow (system, architecture, algorithm and logic). 

%verrous scientifiques et techniques
\vspace*{.9ex}\par
The COACH environment mixes and integrates several hardware and software technologies.
The more important technologies are:
\begin{description}
\item[Design Space Exploration]
    The COACH environment will support design space exploration to help the
    system designer to select and parameterize the target architecture, and to
    define the proper hardware/software partitioning of the application.
    For each point in the design space, metrics such as throughput, latency, power
    consumption, silicon area, memory allocation and data locality will be provided.
    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
    and high-level estimation methodologies.
\item[Hardware Accelerators Synthesis (HAS)]
    COACH will allow the automatic generation of hardware accelerators when required.
    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
    (ASIP) design environment and source-level transformation tools (loop transformations
    and memory optimisation) will be provided.
    This will allow further exploration of the micro-architectural design space.
    HLS tools are sensitive to the coding style of the input specification and the domain
    they target (control vs. data dominated).
    The HLS tools of COACH will support a common language and coding style to avoid
    re-engineering by the designer.
\item[Targeted hardware architecture and technology] 
    COACH will handle both \altera and \xilinx FPGA devices.
    COACH will define architectural templates that can be customized by adding
    dedicated coprocessors and ASIPs and by fixing template parameters such as
    the number of CPU and the operating system.
    Basically, the 3 following architectural templates will be provided:
    \begin{enumerate}
    \item A Neutral architectural template based on the SoCLib IP core library and the
      VCI/OCP communication infrastructure.
    \item An \altera architectural template based on the \altera IP core library and the
      AVALON system bus.
    \item A \xilinx architectural template based on the Xlinx IP core library and the OPB
      system bus.
    \end{enumerate}
    Moreover, the specification of the application will be independant of both the
    architectural template and the target FPGA device.
\item[Communication interfaces]
    Coach will define and implement an homogeneous HW/SW communication infrastructure and
    communication APIs (Application Programming Interface).
    These laters are on-chip communications between processors and coprocessors,
    and external communications between the FPGA and the host PC. 
\end{description}
The COACH design flow will be dedicated to system designers, and will as
much as possible hide the hardware characteristics to the end user.
%From the end user point of view, the specification of the application will be
%independant from both the architectural template and from the selected FPGA
%family.

% le programme de travail
\vspace*{.9ex}\par
%The COACH project targets fundamental issues related to design methodologies for 
%digital systems by providing estimation, exploration and design tools targeting both 
%performance and power optimization at all the abstraction levels of the flow (system, 
%architecture, algorithm and logic).
To reach this ambitious goal, the project will rely on the experience and the
complementariness of partners in the following domains:
Operating system and communication middleware (\tima, \upmc),
MPSoC architectures (\tima, \ubs, \upmc),
ASIP architectures (\irisa),
High Level Synthesis (\tima, \ubs, \upmc) and compilation (\lip).
\\
%The CoACH proposal can be described as an extension of the SoCLib virtual
%prototyping platform to the FPGA technologies.
The COACH project does not start from scratch.
It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
(DSX, component library), operating systems (MutekH, DNA/OS).
It also leverages on  several existing technologies:
on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
on the ROMA~\cite{roma} project for ASIP,
on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
and on the \xilinx and \altera IP core libraries.
Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
bitstreams.
\par
The COACH proposal has been prepared during one year by a technical working group
involving all the academic partners (one monthly meeting from january 2009 to february
2010). The objective of these meetings was to analyse the issues of integrating
and enhancing the formers tools and tecnnologies into a unique framework allowing to both
virtual prototyping and hardware generation.
Because the SocLib platform is the base of this project, it may be described as an
extension of the SoCLib platform.
\par
The main development steps of the COACH project are: 
\begin{enumerate}
   \item Definition of the end user inputs:
    The coarse grain parallelism of the application will be described as a communicating
    task graph, each task being described in C language.
    Similarly the architectural templates with their parameters and the design constraints
    will be specified.
  \item Definition of an internal format for representing task.
  \item Development of the GCC pluggin for generating the internal format of a
    C task.
  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
    the internal format. This will allow to swap from one tool to another one, and to
    chain them if necessary.
  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
    platform to generate the bitstream for the various FPGA families and architectural
    templates.
  \item Development of new tools such as ASIP compiler, HPC design environment and
    dynamic reconfiguration of FPGA devices.
\end{enumerate}
\par
The two major FPGA companies \altera and \xilinx are participating in this
project to support the partners providing the software technologies, and to
help to generate efficient bitsream for both FPGA families.
The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
real use cases to benchmark the COACH design environment.
\par
Following the general policy of the SoCLib platform, the COACH project will be an open
infrastructure, available in the framework of the SoCLib server.
The architectural templates, and the COACH software tools will be distributed under the
GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
IP core library) will be freely available for non commercial use. Commercial licences
will be negociated for industrial exploitation.