source: anr/section-1.tex @ 19

% les objectifs globaux, 
An embedded system is an application integrated into one or several chips
in order to accelerate it or to embedd it into a small device such as a
personal digital assistant (PDA). This topic is investigated since 80s
using Applications Specific Integrated Circuits (ASIC), Digital Signal
Processing (DSP) and parallel computing on multiprocessor machines or
networks.  More recently, since end of 90s, other technologies appeared
like Very Large Instruction Word (VLIW), Application Specific Instruction
Processors (ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC).
\\
During these last decades embedded system was reserved to major industrial
companies targeting high volume market due to the design and fabrication
costs.
Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
and Stratix4 from Altera, can implement a SoC with multiple processors and
several coprocessors for less than 10K euros per item.
In addition, High Level Synthesis (HLS) becomes more mature and allows to
automate design and to drastically decrease its cost in terms of man power.
Thus, both FPGA and HLS tend to spread over HPC for small companies
targeting low volume markets.
\par
To get an efficient embedded system, designer has to take into account
application characteristics when it chooses one of the former technologies.
This choice is not easy and in most cases designer has to try different
technologies to retain the most adapted one.
\\
The first objective of COACH is to provide a framework to
design embedded system on FPGA device.
COACH framework allows designer to explore various software/hardware
partitions of the target application, to run timing and functional
simulations and to generate automatically both the software and the
synthesizable description of the hardware.
The main topics of the project are:
\begin{itemize} 
\item Design space exploration: It consists in analysing the application
runnig on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
hardware/software partitioning of tasks depending on technology choice.
This exploration is driven basically by throughput, latency and power
consumption criteria.
\item Micro-architectural exploration: When hardware components are
required, the HLS tools of the framework generate them automatically. At
this stage the framework provides various HLS tools allowing the
micro-architectural space design exploration. The exploration criteria are
also throughput, latency and power consumption.
% FIXME
%CA At this stage, preliminary source-level transformations will be
%CA required to improve the efficiency of the target component.
%CA COACH will also provide such facilities, such as automatic parallelization
%CA and memory optimisation.
\item Performance measurement: For each point of design space exploration,
metrics of criteria are available such as throughput, latency, power
consumption, area, memory allocation and data locality.
They are evaluated using virtual prototyping, estimation or analysing
methodologies.
\item Targeted hardware technology: The COACH description of system is
independent of the FPGA family.
Every point of the design exploration space can be implemented on any FPGA
having the required resources.
Basically, COACH handles both Altera and Xilinx FPGA families and supports
3 generic target architectures:
the COACH architecture based on the MIPS of the TSAR ANR project and a VCI ring bus,
the Altera architecture based on the NIOS and AVALON bus,
the Xilinx architecture based on the MICROBLAZE and OPB bus.
\end{itemize}
As an extension of embedded system design, COACH deals also with High
Performance Computing (HPC).
In HPC, the kind of targeted application is an existing one running on PC.
COACH helps designer to accelerate it by migrating critical parts into a
SoC implemented on a FPGA plugged to the PC bus.\\
Finally COACH will be developped under the General Public Licence for the software,
and USAGE LIBRE NON COMMERCIAL for the COACH architecture.
%
% verrous scientifiques et techniques
\mbox{}\vspace*{.9ex}\par
System design is a very complicated task and in this project we try to simplify it
as much as possible. For this purpose we have to deal with the following scientific
and technological barriers.
\begin{itemize}
\item The run frequency of the coprocessors generated by the HLS must respect
accurately the system frequency given bt the processors and bus.
\item HLS tools are sensitive to the style in which the algorithm is written
and the domain they target. The HLS tools of COACH must have a common language
and style to avoid engineering work to the designer.
\item The main problem in HPC is in the communication between the PC and the SoC
firstly at the efficiency level and secondly to eliminate enginnering effort to
implement it.
\end{itemize}
%
% le programme de travail
\vspace*{.9ex}\par
COACH is the result of the will of several laboratories to unify their know
hows and skills in the following domains: Operating system and hardware
communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
HLS (LIP6, Lab-STIC and LIP).
So COACH does not starts from scratch but it relies
on SocLib~\cite{soclib} with the MUTEX and DNA/OS operating system for
system prototyping,
on BEE~\cite{bee}, GAUT~\cite{gaut08}, ROMA~\cite{roma}, SYNTOL~\cite{syntol}
and UGH~\cite{ugh08} for HLS.
The project objective is to integrate and enhance these various tools into
a unique free framework masking as much as possible these domains and its
different tools to the system designer.  The main steps of this projects are:
1) Definition of the designer input as set of communicating tasks, each
task beeing described in C++ language.
2) Definition of the xhls format, an internal format for representing a
task.
3) Developping a GCC addon for generating the xhls date from a C++ task
description.
4) Adapting the existing HLS tools to read and write xhls format and
enhancing them. This allows to swap from one tool to the other and
chain them.
5) Modifying the Design System Explorator of SocLib to let the designer
to explore the design space and then to generate the bitstream to
the target FPGA.
\par
The role of the industrials BUL, THALES, XXX, XXX is to provide real
benchmark to guide the design of framework and prove that COACH is
usuable and cover a large spectrum of applications.
%
% les retombées scientifiques, techniques et économiques
\vspace*{.9ex}\par
The main scientific contributions of the project are
firstly to make high level synthesis an elementary tool of system design,
seconly to unify various synthesis techniques (same input and output formats)
allowing the designer to swap from one to an other and even to chain them
without rewritting effort,
and finally to provide a system description independent of the target
architecture and the FPGA family.
\par
The market of embedded system and HPC is about 4,600 M\$ today and is
estimated to 5,600 M\$ in 2012.
This market is dominated by Multi-core CPUs based solution and is controlled
by major companies that can support the very high Non Recurring Engineering (NRE)
costs involved in designing such system.
Small companies can only be present in this market with GPUs based solutions that have
low NRE costs but limit the application domains.\\
COACH reduces the NRE costs to the design costs (the FPGA device being only a few
K\euro) and reduces drastically them.
So one can expect that tools targeting FPGA and dedicated to software developpers
will gain market share over Multi-core CPUs and GPUs HPC based solutions.
Moreover this market can also be boosted by small and even very small new companies
that will be able to propose embedded system and accelerating solutions for standard
software applications with acceptable prices.\\
The two major FPGA companies Altera and Xilinx expect thus by supporting
and participating in this project.