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1% les objectifs globaux,
2The market of digital systems is about 4,600 M\$ today and is estimated to
35,600 M\$ in 2012. However the ever growing applications complexity involves
4integration of heterogeneous technologies and requires the design of
5complex Multi-Processors System on Chip (MPSoC).
6\\
7\mustbecompleted{FIXME :: A relire, j'ai modifie le paragraphe suivant en motivant plus}
8During the last decade, the design of ASICs (Application Specific
9Integrated Circuits) appeared to be more and more reserved to high volume markets, because
10the design and fabrication costs of such components exploded, due to increasing NRE (Non
11Recurring-Engineering) costs.
12Fortunately, FPGA (Field Programmable Gate Array) components, such as the
13Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
14implement a complete MPSoC with multiple processors and several dedicated
15coprocessors for a few Keuros per device. Many applications are initially captured
16algorithmically in High-Level Languages HLLs such as C/C++. This has led to growing interest
17in tools that can provide an implementation path directly from HLLs to hardware.
18Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
19Co-design, High-Level Synthesis...) are now mature and allow the automation of
20a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
21on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
22However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
23methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
24designs written in C/C++ language and implementing the function straight into FPGA.
25We believe that coupling FPGA technologies and ESL methodologies
26will allow both SMEs (Small and Medium Enterprise) and
27major companies to design innovative devices and to enter new, low and
28medium volume markets.
29\parlf
30The objective of COACH is to provide an integrated design flow, based on the
31SoCLib infrastructure~\cite{soclib}, and optimized for the design of
32multi-processors digital systems targeting FPGA devices.
33Such digital systems are generally integrated
34into one or several chips, and there are two types of applications:
35They can be embedded (autonomous) applications
36such as personal digital assistants (PDA), ambiant computing components,
37or wireless sensor networks (WSN).
38They can also be extension boards connected to a PC to accelerate a specific computation,
39as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
40\parlf
41%verrous scientifiques et techniques
42The COACH environment will integrate several hardware and software technologies:
43\begin{description}
44\item[Design Space Exploration:]
45    The COACH environment will support design space exploration to help the
46    system designer to select and parameterize the target architecture, and to
47    define the proper hardware/software partitioning of the application.
48    For each point in the design space, metrics such as throughput, latency, power
49    consumption, silicon area, memory allocation and data locality will be provided.
50    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
51    and high-level estimation methodologies.
52        \mustbecompleted{FIXME :: Question que l'on peut se poser sur DSE : quelle est la nouveaté la dedans ?
53        Doit on parler ici de modele de programmation, de mapping... qui permettent un DSE?}
54       
55\item[Hardware Accelerators Synthesis (HAS):]
56    COACH will allow the automatic generation of hardware accelerators when required.
57    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
58    (ASIP) design environment and source-level transformation tools (loop transformations
59    and memory optimisation) will be provided.
60    This will allow further exploration of the micro-architectural design space.
61    HLS tools are sensitive to the coding style of the input specification and the domain
62    they target (control vs. data dominated).
63    The HLS tools of COACH will support a common language and coding style to avoid
64    re-engineering by the designer.
65\item[Platform based design:] 
66    COACH will handle both \altera and \xilinx FPGA devices.
67    COACH will define architectural templates that can be customized by adding
68    dedicated coprocessors and ASIPs and by fixing template parameters such as
69    the number of embedded processors, the number of sizes of embedded memory banks
70    or the embedded the operating system.
71    However, the specification of the application will be independant of both the
72    architectural template and the target FPGA device.
73    Basically, the 3 following architectural templates will be provided:
74    \begin{enumerate}
75    \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the
76      VCI/OCP communication infrastructure.
77    \item An \altera architectural template based on the \altera IP core library, the
78      AVALON system bus and the NIOS processor.
79    \item A \xilinx architectural template based on the Xilinx IP core library, the PLB
80      system bus and the Microblaze processor.
81    \end{enumerate}
82\item[Hardware/Software communication middleware:]
83    COACH will implement an homogeneous HW/SW communication infrastructure and
84    communication APIs (Application Programming Interface), that will be used for
85    communications between software tasks running on embedded processors and
86    dedicated hardware coprocessors.
87\end{description}
88The COACH design flow will be dedicated to system designers, and will as
89much as possible hide the hardware characteristics to the end-user.
90%From the end user point of view, the specification of the application will be
91%independant from both the architectural template and from the selected FPGA
92%family.
93\parlf
94% le programme de travail
95%The COACH project targets fundamental issues related to design methodologies for
96%digital systems by providing estimation, exploration and design tools targeting both
97%performance and power optimization at all the abstraction levels of the flow (system,
98%architecture, algorithm and logic).
99To reach this ambitious goal, the project will rely on the experience and the
100complementariness of partners in the following domains:
101Operating system and communication middleware (\tima, \upmc),
102MPSoC architectures (\tima, \ubs, \upmc),
103ASIP architectures (\irisa),
104High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip).
105\\
106The COACH project does not start from scratch.
107It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
108
109(DSX, component library), operating systems (MUTEKH, DNA/OS).
110It also leverages on  several existing technologies:
111on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
112on the ROMA~\cite{roma} project for ASIP,
113on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
114and on the \xilinx and \altera IP core libraries.
115Finally it will use the \xilinx and \altera logic and phisical synthesis tools to generate the FPGA configuration
116bitstreams.
117\parlf
118The COACH proposal has been prepared during one year by a technical working group
119involving the 5 academic partners (one monthly meeting from january 2009 to february
1202010). The objective was to analyse the issues of integrating
121and enhancing the existing tools and tecnnologies into a unique framework.
122Most of the general software architecture of the proposed design flow (including the
123exchange format specification) has been define by this working group.
124Because the SoCLib platform is the \mustbecompleted{FIXME Fundation, root, basis a la place de base???} base of this project, it may be described as an
125extension of the SoCLib platform.
126%The main development steps of the COACH project are:
127%\begin{enumerate}
128%   \item Definition of the end user inputs:
129%    The coarse grain parallelism of the application will be described as a communicating
130%    task graph, each task being described in C language.
131%    Similarly the architectural templates with their parameters and the design constraints
132%    will be specified.
133%  \item Definition of an internal format for representing task.
134%  \item Development of the GCC pluggin for generating the internal format of a
135%    C task.
136%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
137%    the internal format. This will allow to swap from one tool to another one, and to
138%    chain them if necessary.
139%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
140%    platform to generate the bitstream for the various FPGA families and architectural
141%    templates.
142%  \item Development of new tools such as ASIP compiler, HPC design environment and
143%    dynamic reconfiguration of FPGA devices.
144%\end{enumerate}
145\parlf
146Two major FPGA companies are involved in the project : \xilinx will contribute
147as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
148providing documentation and development boards. These two companies are strongly motivated
149to help the COACH project to generate efficient bitsreams for both FPGA families.
150The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
151real use cases to benchmark the COACH design environment and to analyze the designer productivity
152imrovments. \mustbecompleted{FIXME :: j'ai ajoute "and to analyze..." OK ?} \mustbecompleted{FIXME :: FlexRAS
153sont fournisseur de techno et non de uses cases no ???}
154\parlf
155Following the general policy of the SoCLib platform, the COACH project will be an open
156infrastructure, available in the framework of the SoCLib server.
157The architectural templates, and the COACH software tools will be distributed under the
158GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
159IP core library) will be freely available for non commercial use. For industrial exploitation
160the technology providers are ready to propose commercial licenses, directly to the end user,
161or through a third party.
162
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