source: anr/section-1.tex @ 283

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1% les objectifs globaux,
2The market of digital systems is about 4,600 M\$ today and is estimated to
35,600 M\$ in 2012. However the ever growing applications complexity involves
4integration of heterogeneous technologies and requires the design of
5complex Multi-Processors System on Chip (MPSoC).
6\\
7During the last decade, the design of ASICs (Application Specific
8Integrated Circuits) appeared to be more and more reserved to high volume markets, because
9the design and fabrication costs of such components exploded, due to increasing NRE (Non
10Recurring-Engineering) costs.
11Fortunately, FPGA (Field Programmable Gate Array) components, such as the
12Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
13implement a complete MPSoC with multiple processors and several dedicated
14coprocessors for a few Keuros per device.
15\\
16Many applications are initially captured
17algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
18in tools that can provide an implementation path directly from HLLs to hardware.
19Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
20Co-design, High-Level Synthesis...) are now mature and allow the automation of
21a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
22on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
23However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
24methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
25designs written in C/C++ language and implementing the function straight into FPGA.
26We believe that coupling FPGA technologies and ESL methodologies
27will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
28devices and to enter new, low and medium volume markets.
29\begin{ADDEDENV}
30Furthermore, today there is an increasing industrial interest to IC
31that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
32such as ATOM E600C (Intel).
33Probably in few years, one can expect that such chips will become current and even standard
34general purpose CPU cores will contains a configurable area making explode the low and medium volume
35markets of digital systems.
36\end{ADDEDENV}
37\parlf
38\begin{SUPPRESSEDENV}
39The objective of COACH is to provide an integrated design flow, based on the
40SoCLib infrastructure~\cite{soclib}, and optimized for the design of
41multi-processors digital systems targeting FPGA devices.
42The digital systems are generally integrated into one or several chips, and there are two types of applications:
43They can be embedded (autonomous) applications
44such as personal digital assistants (PDA), ambient computing components,
45or wireless sensor networks (WSN).
46They can also be extension boards connected to a PC to accelerate a specific computation,
47as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
48\end{SUPPRESSEDENV}\begin{ADDEDENV}
49The objective of COACH is to provide an integrated design flow for the design of
50multi-processors digital systems targeting FPGA devices.
51It will be dedicated to system/software designers, and hide as much as possible
52the hardware characteristics to the end-user.
53COACH will mainly target three kinds of digital systems:
541) embedded and autonomous application such as  personal digital assistants (PDA),
55   ambient computing components, or wireless sensor networks (WSN);
562) PCI/E extension boards connected to a PC to accelerate a specific application,
57   it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
583) sub-system application for generating an IP to a larger system.
59\end{ADDEDENV}
60\parlf
61%verrous scientifiques et techniques
62The COACH environment will integrate several hardware and software technologies:
63\begin{description}
64\item[Design Space Exploration:]
65    The COACH environment will allow to describe an application as a process
66        network i.e. a set of tasks communicating through FIFO channels.
67        COACH will allow to map the application on a shared-memory, MPSoC architecture.
68    It will permit to easily explore the design space to help the system designer
69        to define the proper hardware/software partitioning of the application.
70    For each point in the design space, metrics such as throughput, latency, power
71    consumption, silicon area, memory allocation and data locality will be provided.
72    \begin{SUPPRESSEDENV}
73    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
74    and high-level estimation methodologies.
75    \end{SUPPRESSEDENV}
76\item[Hardware Accelerators Synthesis (HAS):]
77    COACH will allow the automatic generation of hardware accelerators when required.
78    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
79    (ASIP) design environment and source-level transformation tools (loop transformations
80    and memory optimization) will be provided.
81    This will allow further exploration of the micro-architectural design space.
82    HLS tools are sensitive to the coding style of the input specification and the domain
83    they target (control vs. data dominated).
84    The HLS tools of COACH will support a common language and coding style to avoid
85    re-engineering by the designer.
86\item[Platform based design:] 
87    COACH will handle both \altera and \xilinx FPGA devices.
88    COACH will define architectural templates that can be customized by adding
89    dedicated coprocessors and ASIPs and by fixing template parameters such as
90    the number of embedded processors, the number of sizes of embedded memory banks
91    or the embedded operating system.
92    However, the specification of the application will be independent of both the
93    architectural template and the target FPGA device.
94    Basically, the following three architectural templates will be provided:
95    \begin{enumerate}
96    \item A Neutral architectural template based on the SoCLib IP core library and the
97      VCI/OCP communication infrastructure.
98    \item An \altera architectural template based on the \altera IP core library, the
99      AVALON system bus and the NIOS processor.
100    \item A \xilinx architectural template based on the \xilinx IP core library, the PLB
101      system bus and the Microblaze processor.
102    \end{enumerate}
103\item[Hardware/Software communication middleware:]
104    COACH will implement an homogeneous HW/SW communication infrastructure and
105    communication APIs (Application Programming Interface), that will be used for
106    communications between software tasks running on embedded processors and
107    dedicated hardware coprocessors.
108\begin{ADDEDENV}
109\item[Interaction with the industrial world]
110    COACH will not be a closed framework but it will be opened to the industrial
111    world by using the IP-XACT format \ref{IP-XACT-08} for describing the components of the
112    architectural template and by providing the IP-XACT description of the generated MPSoC.
113    This should facilitate the enhancement of the architectural template with IP and the
114    integration of the IP produced by COACH in larger design.
115\end{ADDEDENV}
116\end{description}
117\begin{SUPPRESSEDENV}
118MOVED ABOVE
119The COACH design flow will be dedicated to system designers, and will as
120much as possible hide the hardware characteristics to the end-user.
121\end{SUPPRESSEDENV}
122%From the end user point of view, the specification of the application will be
123%independant from both the architectural template and from the selected FPGA
124%family.
125\parlf
126% le programme de travail
127%The COACH project targets fundamental issues related to design methodologies for
128%digital systems by providing estimation, exploration and design tools targeting both
129%performance and power optimization at all the abstraction levels of the flow (system,
130%architecture, algorithm and logic).
131To reach this ambitious goal, the project will rely on the experience and the
132complementariness of partners in the following domains:
133Operating system and communication middleware (\tima, \upmc),
134MPSoC architectures (\tima, \ubs, \upmc),
135ASIP architectures (\irisa),
136High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
137HPC (\bull, \thales), \mustbecompleted{XXX (\mds)}.
138\\
139The COACH project does not start from scratch.
140\begin{SUPPRESSEDENV}
141It strongly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
142(DSX, component library), operating systems (MUTEKH, DNA/OS).
143It also leverages on  several existing technologies:
144on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
145on the ROMA~\cite{roma} project for ASIP,
146on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
147and on the \xilinx and \altera IP core libraries.
148\end{SUPPRESSEDENV}\begin{ADDEDENV}
149It relies
150on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
151on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
152on the ROMA~\cite{roma} project for ASIP,
153on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
154transformations,
155on the \mustbecompleted{XXXX:magillem} for \mustbecompleted{XXXX:magillem},
156and on the \xilinx and \altera IP core libraries.
157\end{ADDEDENV}
158Finally it will use the \xilinx and \altera logic and physical synthesis tools
159to generate the FPGA configuration bitstreams.
160\parlf
161The COACH proposal has been prepared during one year by a technical working group
162involving the 5 academic partners (one monthly meeting from january 2009 to february
1632010). The objective was to analyse the issues of integrating
164and enhancing the existing tools and technologies into a unique framework.
165Most of the general software architecture of the proposed design flow (including the
166exchange format specification) has been define by this working group.
167\SUPPRESSED{Because the COACH project leanes on the ANR SoCLib platform, it may be
168described as an extension of the SoCLib platform.}
169%The main development steps of the COACH project are:
170%\begin{enumerate}
171%   \item Definition of the end user inputs:
172%    The coarse grain parallelism of the application will be described as a communicating
173%    task graph, each task being described in C language.
174%    Similarly the architectural templates with their parameters and the design constraints
175%    will be specified.
176%  \item Definition of an internal format for representing task.
177%  \item Development of the GCC pluggin for generating the internal format of a
178%    C task.
179%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
180%    the internal format. This will allow to swap from one tool to another one, and to
181%    chain them if necessary.
182%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
183%    platform to generate the bitstream for the various FPGA families and architectural
184%    templates.
185%  \item Development of new tools such as ASIP compiler, HPC design environment and
186%    dynamic reconfiguration of FPGA devices.
187%\end{enumerate}
188\parlf
189Two major FPGA companies are involved in the project: \xilinx will contribute
190as a contractual partner providing documentation and manpower; \altera will contribute as
191a supporter (see letter page \pageref{supp:1})
192providing documentation and development boards. These two companies are strongly motivated
193to help the COACH project to generate efficient bitstreams for both FPGA families.
194The role of the industrial partners \bull, \thales and \mds is to provide
195real use cases to benchmark the COACH design environment and to analyze the designer productivity
196improvements.
197\parlf
198\begin{SUPPRESSEDENV}
199Following the general policy of the SoCLib platform, the COACH project will be an open
200infrastructure, available in the framework of the SoCLib server.
201The architectural templates, and the COACH software tools will be distributed under the
202GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
203IP core library) will be freely available for non commercial use.
204\end{SUPPRESSEDENV}\begin{ADDEDENV}
205The COACH project will be an open infrastructure and freely distributed.
206The architectural templates and the COACH software tools will be distributed under the
207GPL license. The VHDL synthesizable models for the neutral architectural template
208will also be freely available for non commercial use.
209\end{ADDEDENV}
210For industrial exploitation the technology providers are ready to propose commercial licenses,
211directly to the end user, or through a third party.
212\parlf
213\mustbecompleted{LIST NON A JOUR}
214Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the
215"letters of interest" (see Annex B), that have collected during the preparation of the project :
216ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL,
217ABOUND Logic, EADS-ASTRIUM.
218
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