source: anr/section-1.tex @ 32

Last change on this file since 32 was 31, checked in by coach, 15 years ago

Première révision de la section 1.
Paul

anr/section-1.tex
anr/section-3.1.tex

File size: 8.7 KB
Line 
1% les objectifs globaux,
2During the last decades, the design of complex digital systems is more and more reserved to the
3high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs
4due to increasing NRE (Non Recurring-Engineering) costs. The market of digital systems is about
54,600 M\$ today and is estimated to 5,600 M\$ in 2012.
6Digital system design has been investigated since the eighties for Application
7Specific Integrated Circuits (ASIC), Digital Signal Processors (DSP) and parallel computing on
8multiprocessor machines or networks.  Other technologies appeared like Very Large
9Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP).
10Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies
11and thus requieres the design of System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
12Nowadays, Field Programmable Gate Arrays (FPGA), such as the Virtex5 from Xilinx
13or the Stratix4 from Altera, can implement a complete SoC with multiple processors and
14several coprocessors for less than 10K euros per device.
15In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
16Co-design, High-Level Synthesis...) is now mature and allow the automation of the design of digital
17systems and drastically decrease their cost in terms of manpower.
18Thus, coupling both FPGA and ESL methodologies will soon allow small and medium
19enterprises (SMEs) and major companies to get into new, low and medium volume markets,
20to design highly innovative devices and to prototype complete digital systems.
21\par
22The objective of COACH is to provide a consolidated flow, integrated and optimized for the design of
23complex digital systems on FPGA devices.  A digital system is an application integrated into one or
24several chips. These chips can be embedded in devices such as a personal digital assistant (PDA),
25an ambiant computing component or a wireless sensor network (WSN). They can also be used on a board connected
26to a PC to accelerate an application as in High-Performance Computing (HPC) or in High-Speed Signal
27Processing (HSSP).
28
29COACH will reduce the NRE costs to the design costs (the FPGA device being only a few
30K\euro) and drastically reduces them. If proper tools, better suited to
31softaware developers are created, one
32can expect that FPGA based devices
33will gain market share over Multi-core CPUs and GPUs HPC based solutions.
34Moreover this market can also be boosted by small and even very small new companies
35that will be able to propose embedded system and accelerating solutions for standard
36software applications with acceptable prices.\\
37
38The main idea is to increase the design productivity by selecting a given flexible architectural template
39and targeting the area of complex digital systems. This project involves the development of methodologies and
40tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC)
41of whole systems, while taking into account different application constraints (power consumption, throughput, latency...).
42The project will also optimize an
43important interface, usually not taken into account, between the high-level synthesis and the implementation
44techniques on physical targets and the associated low level tools (logic synthesis and compilation).
45The design flow will allow, from a high-level specification (written in the C language), to estimate, analyze, optimize the
46performances and then implement a real architecture. The COACH framework will allow the designer to explore various
47software/hardware partitioning scenario for the target application through timing and functional simulations and to
48generate automatically both the software and the synthesizable description of the hardware.
49
50%verrous scientifiques et techniques
51The main contributions of the project are:
52\begin{itemize} 
53\item Targeted hardware architecture and technology:
54COACH will handle both Altera and Xilinx FPGA technologies. COACH will define
55architectural templates that can be customized by additional dedicated coprocessors and ASIPs.
56The parameters of the architectural templates will be the number of CPU, the operating  system... 
57%the coprocessors, the number and the size of the FIFO communication channels
58Basically, the 3 following architectural templates will be provided:
59\begin{itemize}
60\item A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
61\item An Altera architectural template based on the NIOS and the AVALON bus,
62%FIXME
63% The following point has to be confirmed by XILINX
64% Microblaze+OPB => ARM+Amba ???
65\item A Xilinx architectural template based on the MICROBLAZE and the OPB bus.
66\end{itemize}
67Moreover, the specification of the application will be independant of both the template
68architecture and the selected technology.
69\item Design space exploration: The COACH environment will allow the selection and parametrization of
70the target architecture, the definition of the hardware/software partitioning and the profiling of the application.
71For each point in the design space, metrics such as throughput, latency, power consumption,
72silicon area, memory allocation and data locality will be provided.
73This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
74\item Hardware accelerators synthesis (HAS): COACH will allow the automatic generation of hardware accelerators
75when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and
76source-level transformations (loop transformations and memory optimisation) will be provided.
77This will allow further exploration of the micro-architectural design space.
78HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs.
79data dominated). The HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer.
80\item Communication interface: Coach will define and implement HW/SW communication management and define APIs
81enabling communication between processors, processor/coprocessors,  FPGA and PC.
82\end{itemize}
83%In HPC, the kind of targeted application is an existing one running on PC.
84%COACH helps designer to accelerate it by migrating critical parts into a
85%SoC implemented on a FPGA plugged to the PC bus.\\
86%FIXME licence a speficier
87
88The COACH tools will be designed to hide the hardware as much as possible from the end user.
89It will thus be mainly dedicated to system designers.
90
91
92
93% le programme de travail
94\vspace*{.9ex}\par
95
96The COACH project targets fundamental issues related to design methodologies for
97digital systems by providing estimation, exploration and design tools targeting both
98performance and power optimization at all the abstraction levels of the flow (system,
99architecture, algorithm and logic).
100
101To reach this ambitious aim, this project will lean on the experience and the complementariness
102of partners in the following domains: Operating system and hardware
103communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
104HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
105COACH does not start from scratch but relies
106on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for
107SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on
108ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
109
110The project objective is to enhance and seamlessly integrate these tools into
111a unique open source framework.
112The main steps of this project are:
1131) Definition of the user inputs: application description as set of communicating tasks, each
114task beeing described in the C++ language; architectural template with its parameters; design constraints.
1152) Definition of the internal \xcoach format for representing a task.
1163) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
1174) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to
118swap from one tool to another one and to chain them.
1195) Modification of the Design System eXplorator (DSX) of the SocLib platform to let the user
120explore the design space and then to generate the bitstream.
121%FIXME : a completer
122\par
123
124The two major FPGA companies Altera and Xilinx expect this by supporting
125and participating in this project.
126The role of the industrial partners BULL, THALES, XXX is to provide real
127benchmarks to guide the design of the framework and to prove that COACH is
128usuable and cover a large spectrum of applications.
129
130The COACH arhitectural templates will be freely distributed for non commercial use.
131The software tools of COACH will be developped under the General Public Licence.
132
Note: See TracBrowser for help on using the repository browser.