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1% les objectifs globaux,
2The market of digital systems is about 4,600 M\$ today and is estimated to
35,600 M\$ in 2012. However the ever growing applications complexity involves
4higher integration of heterogeneous technologies and requires the design of
5complex Multi-Processors System on Chip (MPSoC).
6During the last decade, the design of complex digital ASICs (Application Specific
7Integrated Circuits) appeared to be more and more reserved to high volume markets, because
8the design and fabrication costs of such components exploded, due to increasing NRE (Non
9Recurring-Engineering) costs.
10\\
11FPGA (Field Programmable Gate Array) components, such as the
12Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
13implement a complete MPSoC with multiple processors and several
14coprocessors for a few keuros per device.
15In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
16Co-design, High-Level Synthesis...) are now mature and allow the automation of
17a system level design flow that targets FPGA devices.
18We believe that coupling FPGA technologies and ESL methodologies
19will allow both SMEs (Small and Medium Enterprise) and
20major companies to design innovative devices and to enter new, low and
21medium volume markets.
22\\
23The objective of COACH is to provide an integrated design flow, based on the
24SoCLib infrastructure~\cite{soclib}, and optimized for the design of
25multi-processors digital systems targetting FPGA devices.
26Such digital systems are generally integrated
27into one or several chips, and there are two types of applications:
28It can be embedded (autonomous) applications
29such as personal digital assistants (PDA), ambiant computing components
30or wireless sensor networks (WSN)
31They can also be extension boards connected to a PC to accelerate a specific computation,
32as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
33\\
34The COACH project fundamental issues are related to design methodologies
35for digital systems, providing estimation, exploration and design tools
36targeting both performance and power optimization at all the abstraction
37levels of the flow (system, architecture, algorithm and logic).
38
39%verrous scientifiques et techniques
40\vspace*{.9ex}\par
41The COACH environment mixes and integrates several hardware and software technologies.
42The more important technologies are:
43\begin{description}
44\item[Design Space Exploration]
45    The COACH environment will support design space exploration to help the
46    system designer to select and parameterize the target architecture, and to
47    define the proper hardware/software partitioning of the application.
48    For each point in the design space, metrics such as throughput, latency, power
49    consumption, silicon area, memory allocation and data locality will be provided.
50    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
51    and high-level estimation methodologies.
52\item[Hardware Accelerators Synthesis (HAS)]
53    COACH will allow the automatic generation of hardware accelerators when required.
54    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
55    (ASIP) design environment and source-level transformation tools (loop transformations
56    and memory optimisation) will be provided.
57    This will allow further exploration of the micro-architectural design space.
58    HLS tools are sensitive to the coding style of the input specification and the domain
59    they target (control vs. data dominated).
60    The HLS tools of COACH will support a common language and coding style to avoid
61    re-engineering by the designer.
62\item[Targeted hardware architecture and technology] 
63    COACH will handle both \altera and \xilinx FPGA devices.
64    COACH will define architectural templates that can be customized by adding
65    dedicated coprocessors and ASIPs and by fixing template parameters such as
66    the number of CPU and the operating system.
67    Basically, the 3 following architectural templates will be provided:
68    \begin{enumerate}
69    \item A Neutral architectural template based on the SoCLib IP core library and the
70      VCI/OCP communication infrastructure.
71    \item An \altera architectural template based on the \altera IP core library and the
72      AVALON system bus.
73    \item A \xilinx architectural template based on the Xlinx IP core library and the OPB
74      system bus.
75    \end{enumerate}
76    Moreover, the specification of the application will be independant of both the
77    architectural template and the target FPGA device.
78\item[Communication interfaces]
79    Coach will define and implement an homogeneous HW/SW communication infrastructure and
80    communication APIs (Application Programming Interface).
81    These laters are on-chip communications between processors and coprocessors,
82    and external communications between the FPGA and the host PC.
83\end{description}
84The COACH design flow will be dedicated to system designers, and will as
85much as possible hide the hardware characteristics to the end user.
86%From the end user point of view, the specification of the application will be
87%independant from both the architectural template and from the selected FPGA
88%family.
89
90% le programme de travail
91\vspace*{.9ex}\par
92%The COACH project targets fundamental issues related to design methodologies for
93%digital systems by providing estimation, exploration and design tools targeting both
94%performance and power optimization at all the abstraction levels of the flow (system,
95%architecture, algorithm and logic).
96To reach this ambitious goal, the project will rely on the experience and the
97complementariness of partners in the following domains:
98Operating system and communication middleware (\tima, \upmc),
99MPSoC architectures (\tima, \ubs, \upmc),
100ASIP architectures (\irisa),
101High Level Synthesis (\tima, \ubs, \upmc) and compilation (\lip).
102\\
103%The CoACH proposal can be described as an extension of the SoCLib virtual
104%prototyping platform to the FPGA technologies.
105The COACH project does not start from scratch.
106It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
107(DSX, component library), operating systems (MutekH, DNA/OS).
108It also leverages on  several existing technologies:
109on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
110on the ROMA~\cite{roma} project for ASIP,
111on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
112and on the \xilinx and \altera IP core libraries.
113Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
114bitstreams.
115\par
116The COACH proposal has been prepared during one year by a technical working group
117involving all the academic partners (one monthly meeting from january 2009 to february
1182010). The objective of these meetings was to analyse the issues of integrating
119and enhancing the formers tools and tecnnologies into a unique framework allowing to both
120virtual prototyping and hardware generation.
121Because the SocLib platform is the base of this project, it may be described as an
122extension of the SoCLib platform.
123\par
124The main development steps of the COACH project are:
125\begin{enumerate}
126   \item Definition of the end user inputs:
127    The coarse grain parallelism of the application will be described as a communicating
128    task graph, each task being described in C language.
129    Similarly the architectural templates with their parameters and the design constraints
130    will be specified.
131  \item Definition of an internal format for representing task.
132  \item Development of the GCC pluggin for generating the internal format of a
133    C task.
134  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
135    the internal format. This will allow to swap from one tool to another one, and to
136    chain them if necessary.
137  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
138    platform to generate the bitstream for the various FPGA families and architectural
139    templates.
140  \item Development of new tools such as ASIP compiler, HPC design environment and
141    dynamic reconfiguration of FPGA devices.
142\end{enumerate}
143\par
144The two major FPGA companies \altera and \xilinx are participating in this
145project to support the partners providing the software technologies, and to
146help to generate efficient bitsream for both FPGA families.
147The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
148real use cases to benchmark the COACH design environment.
149\par
150Following the general policy of the SoCLib platform, the COACH project will be an open
151infrastructure, available in the framework of the SoCLib server.
152The architectural templates, and the COACH software tools will be distributed under the
153GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
154IP core library) will be freely available for non commercial use. Commercial licences
155will be negociated for industrial exploitation.
156
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