1 | Microelectronic components allow the integration of complicated functions into products, increases |
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2 | commercial attractivity of these products and improves their competitivity. |
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3 | Multimedia and tele-communication sectors have taken advantage from microelectronics facilities |
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4 | thanks to the developpment of design methodologies and tools for embedded systems. |
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5 | \par |
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6 | Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing |
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7 | and manufacturing ASICs is very high. |
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8 | An IC foundry costs several billions of euros and the fabrication of a specific circuit |
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9 | costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 |
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10 | million USD. |
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11 | Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium |
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12 | volume markets. |
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13 | \par |
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14 | Today, FPGAs become important actors in the computational domain that was originally dominated |
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15 | by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed |
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16 | on a per-application basis. For many applications, FPGAs offer significant performance benefits over |
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17 | microprocessors implementation. There is still a performance degradation of one order |
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18 | of magnitude versus an equivalent ASIC implementations, but low cost |
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19 | (500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive |
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20 | choice for low-to-medium volume applications. |
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21 | Since their introduction in the mid eighties, FPGAs evolved from a simple, |
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22 | low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that |
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23 | provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, |
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24 | on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement |
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25 | complex systems like multi-processors platform with application dedicated coprocessors. |
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26 | Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in |
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27 | various application domains. |
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28 | This market is in significant expansion and is estimated to 914\,M\$ in 2012. |
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29 | |
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30 | \begin{table}\leavevmode\center |
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31 | \begin{tabular}{|l|l|l|l|}\hline |
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32 | Segment & 2010 & 2011 & 2012 \\\hline\hline |
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33 | Communications & 1,867 & 1,946 & 2,096 \\ |
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34 | High end & 467 & 511 & 550 \\\hline |
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35 | Consumer & 550 & 592 & 672 \\ |
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36 | High end & 53 & 62 & 75 \\\hline |
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37 | Automotive & 243 & 286 & 358 \\ |
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38 | High end & - & - & - \\\hline |
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39 | Industrial & 1,102 & 1,228 & 1,406 \\ |
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40 | High end & 177 & 188 & 207 \\\hline |
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41 | Military/Aereo & 566 & 636 & 717 \\ |
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42 | High end & 56 & 65 & 82 \\\hline\hline |
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43 | Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ |
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44 | Total High-End FPGA & 753 & 826 & 914 \\\hline |
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45 | \end{tabular} |
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46 | \caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} |
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47 | \end{table} |
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48 | \par |
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49 | |
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50 | This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions |
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51 | is limited by the lack of design flow automation. Nowadays, there are neither commercial |
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52 | nor academic tools covering the whole design process from the system level specification to the bit stream |
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53 | generation. |
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54 | %For instance, with SOPC Builder from Altera, users can select and parameterize IP components |
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55 | %from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor |
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56 | %and bus interface cores, as well as incorporate their own IP. Designers can then generate |
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57 | %a synthesized netlist, simulation test bench and custom software library that reflect the hardware |
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58 | %configuration. |
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59 | %Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I |
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60 | (%Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to |
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61 | %simulate the platform at a high design level (systemC). |
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62 | %In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation |
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63 | %tool to implement designs on Altera devices (Stratix, Arria, Cyclone). |
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64 | %PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. |
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65 | %Nevertheless, they can only deal with data dominated applications and they do not handle the platform level. |
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66 | %The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to |
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67 | %Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. |
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68 | %Designers can design and simulate a system using MATLAB and Simulink. The tool will then |
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69 | %automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx |
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70 | %pre-optimized algorithms. |
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71 | %However, this tool targets only DSP based algorithms. |
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72 | |
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73 | Consequently, a designer developping an embedded system needs to master |
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74 | four different design environment : a virtual prototyping environment such as SoCLib for system level exploration, |
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75 | an architecture compiler (such as SOPC Builder from Altera, or System generator from Xilinx) to define the |
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76 | hardware architecture, one or several HLS tools (such as PICO [CITATION] ou CATAPULT [CITATION]) for |
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77 | coprocessor synthesis, and finally a backend synthesis tool (such as Quartus or YYYY) for the bit-stream generation. |
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78 | |
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79 | The aim of the COACH project is to integrate all these design steps into a single design framework. |
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80 | and to allow \textbf{pure software} developpers to develop embedded systems. |
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81 | \par |
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82 | We believe that the combination of a design environment dedicated to software developpers and the FPGA target, |
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83 | allows small and even very small companies to propose embedded system and accelerating solutions |
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84 | for standard software applications with acceptable prices. |
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85 | |
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86 | This new market may explode in the same way as the micro-computer market in the eighties, |
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87 | whose success was due to the low cost of the first micro-processors (compared to main frames) |
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88 | and the advent of high level programming languages which allowed a high number of programmers |
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89 | to launch start-ups in software engineering. |
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90 | |
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