1 | Microelectronic allows the integration of complicated functions into products, increases |
---|
2 | commercial attractivity of these products and improves their competitivity. |
---|
3 | Multimedia and communication sectors have taken advantage from microelectronics facilities |
---|
4 | thanks to the developpment of design methodologies and tools for real time embedded |
---|
5 | systems. |
---|
6 | Many other sectors could benefit from microelectronics if these methologies and tools were |
---|
7 | adapted to their features. The Non Recurring Engineering (NRE) costs involded in designing |
---|
8 | and manufacturing an ASIC is very high. |
---|
9 | An IC foundry costs several billions of euros and the fabrication of a specific circuit |
---|
10 | costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 |
---|
11 | million USD. |
---|
12 | Consequently, it is generally unfeasible to design and fabricate ASICs in |
---|
13 | low volumes and ICs are designed to cover a broad applications spectrum at the cost of |
---|
14 | some performance degradation. |
---|
15 | \\ |
---|
16 | Today, FPGAs become important actors in the computational domain that was originally dominated |
---|
17 | by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed |
---|
18 | on a per-application basis. At the same time, for many applications, FPGAs offer significant performance benefits over |
---|
19 | microprocessors implementation. Although these benefits are still |
---|
20 | generally an order of magnitude less than in equivalent ASIC implementations, low costs |
---|
21 | (500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive |
---|
22 | choice for low-to-medium volume applications. |
---|
23 | Since their introduction in the mid eighties, FPGAs evolved from a simple, |
---|
24 | low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that |
---|
25 | provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, |
---|
26 | on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement |
---|
27 | complex systems like multi-processors platform with application dedicated coprocessors. |
---|
28 | Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in |
---|
29 | various application domains. The ``high end'' lines concern only FPGA with high logic capacity for complex system implementations. |
---|
30 | This market is in significant expansion and is estimated to 914\,M\$ in 2012. |
---|
31 | Using FPGA limits the NRE costs to the design cost. This boosts the developpment of of automatic design tools and methodologies. |
---|
32 | |
---|
33 | \begin{table}\leavevmode\center |
---|
34 | \begin{tabular}{|l|l|l|l|}\hline |
---|
35 | Segment & 2010 & 2011 & 2012 \\\hline\hline |
---|
36 | Communications & 1,867 & 1,946 & 2,096 \\ |
---|
37 | High end & 467 & 511 & 550 \\\hline |
---|
38 | Consumer & 550 & 592 & 672 \\ |
---|
39 | High end & 53 & 62 & 75 \\\hline |
---|
40 | Automotive & 243 & 286 & 358 \\ |
---|
41 | High end & - & - & - \\\hline |
---|
42 | Industrial & 1,102 & 1,228 & 1,406 \\ |
---|
43 | High end & 177 & 188 & 207 \\\hline |
---|
44 | Military/Aereo & 566 & 636 & 717 \\ |
---|
45 | High end & 56 & 65 & 82 \\\hline\hline |
---|
46 | Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ |
---|
47 | Total High-End FPGA & 753 & 826 & 914 \\\hline |
---|
48 | \end{tabular} |
---|
49 | \caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} |
---|
50 | \end{table} |
---|
51 | \par |
---|
52 | Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, |
---|
53 | Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand |
---|
54 | for very high performance (HPC) primes over other requirements. They tend to use the highest |
---|
55 | performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative |
---|
56 | architectures and algorithms. These companies show up in different "traditional" applications and market |
---|
57 | segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC |
---|
58 | emulation and prototyping, Mil/aero etc. The HPC market size is estimated today by FPGA providers |
---|
59 | at 214\,M\$. |
---|
60 | This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion |
---|
61 | of FPGA-based solutions is limited by the lack of design flow automation. Nowadays, there are neither commercial |
---|
62 | nor academic tools covering the whole design process. |
---|
63 | For instance, with SOPC Builder from Altera, users can select and parameterize IP components |
---|
64 | from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor |
---|
65 | and bus interface cores, as well as incorporate their own IP. Designers can then generate |
---|
66 | a synthesized netlist, simulation test bench and custom software library that reflect the hardware |
---|
67 | configuration. |
---|
68 | Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I |
---|
69 | (Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to |
---|
70 | simulate the platform at a high design level (systemC). |
---|
71 | In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation |
---|
72 | tool to implement designs on Altera devices (Stratix, Arria, Cyclone). |
---|
73 | PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. |
---|
74 | Nevertheless, they can only deal with data dominated applications and they do not handle the platform level. |
---|
75 | The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to |
---|
76 | Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. |
---|
77 | Designers can design and simulate a system using MATLAB and Simulink. The tool will then |
---|
78 | automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx |
---|
79 | pre-optimized algorithms. |
---|
80 | However, this tool targets only DSP based algorithms. |
---|
81 | \\ |
---|
82 | Consequently, designers developping an embedded system needs to master for example |
---|
83 | SoCLib for design exploration, |
---|
84 | SOPC Builder at the platform level, |
---|
85 | PICO for synthesizing the data dominated coprocessors |
---|
86 | and Quartus for design implementation. |
---|
87 | This requires an important tools interfacing effort and makes the design process very complex |
---|
88 | and achievable only by designers skilled in many domains. |
---|
89 | The aim of the COACH project is to integrate all these tools in the same framework and to allow \textbf{pure software} developpers to realize embedded systems. |
---|
90 | \par |
---|
91 | The combination of the framework dedicated to software developpers and FPGA target, allows to gain |
---|
92 | market share over Multi-core CPUs and GPUs HPC based solutions. |
---|
93 | Moreover, one can expect that small and even very small companies will be able to propose embedded |
---|
94 | system and accelerating solutions for standard software applications with acceptable prices, thanks |
---|
95 | to the elimination of huge hardware investment in opposite to ASIC based solution. |
---|
96 | \\ |
---|
97 | This new market may explode in the same way as the micro-computer market in the eighties. This success was due |
---|
98 | to the low cost of the first micro-processors (compared to main frames) and the advent of high level |
---|
99 | programming languages which allowed a high number of programmers to launch start-ups in software |
---|
100 | engineering. |
---|
101 | |
---|