source: anr/section-2.1.tex @ 56

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Modifications de TIMA, task-5 et section-3.1 principalement

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1Microelectronic allows the integration of complicated functions into products, increases
2commercial attractivity of these products and improves their competitivity.
3Multimedia and communication sectors have taken advantage from microelectronics facilities
4thanks to the developpment of design methodologies and tools for real time embedded
5systems.
6Many other sectors could benefit from microelectronics if these methologies and tools were
7adapted to their features. The Non Recurring Engineering (NRE) costs involded in designing
8and manufacturing an ASIC is very high.
9An IC foundry costs several billions of euros and the fabrication of a specific circuit
10costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
11million USD.
12Consequently, it is generally unfeasible to design and fabricate ASICs in
13low volumes and ICs are designed to cover a broad applications spectrum at the cost of
14some performance degradation.
15\\
16Today, FPGAs become important actors in the computational domain that was originally dominated
17by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
18on a per-application basis. At the same time, for many applications, FPGAs offer significant performance benefits over
19microprocessors implementation. Although these benefits are still
20generally an order of magnitude less than in equivalent ASIC implementations, low costs
21(500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive
22choice for low-to-medium volume applications.
23Since their introduction in the mid eighties, FPGAs evolved from a simple,
24low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that
25provide a mix of coarse-grained data path units, memory blocks, microprocessor cores,
26on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
27complex systems like multi-processors platform with application dedicated coprocessors.
28Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
29various application domains. The ``high end'' lines concern only FPGA with high logic capacity for complex system implementations.
30This market is in significant expansion and is estimated to 914\,M\$ in 2012.
31Using FPGA limits the NRE costs to the design cost. This boosts the developpment of of automatic design tools and methodologies.
32
33\begin{table}\leavevmode\center
34\begin{tabular}{|l|l|l|l|}\hline
35Segment         & 2010  & 2011  & 2012 \\\hline\hline
36Communications  & 1,867 & 1,946 & 2,096 \\
37High end        & 467   & 511   & 550 \\\hline
38Consumer        & 550   & 592   & 672 \\
39High end        & 53    & 62    & 75 \\\hline
40Automotive      & 243   & 286   & 358 \\
41High end        & -     & -     & - \\\hline
42Industrial      & 1,102 & 1,228 & 1,406 \\
43High end        & 177   & 188   & 207 \\\hline
44Military/Aereo  & 566   & 636   & 717 \\
45High end        & 56    & 65    & 82 \\\hline\hline
46Total FPGA/PLD  & 4,659 & 5,015 & 5,583 \\
47Total High-End  FPGA    & 753   & 826   & 914 \\\hline
48\end{tabular}
49\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
50\end{table}
51\par
52Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
53Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
54for very high performance (HPC) primes over other requirements. They tend to use the highest
55performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
56architectures and algorithms. These companies show up in different "traditional" applications and market
57segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
58emulation and prototyping, Mil/aero etc. The HPC market size is estimated today by FPGA providers
59at 214\,M\$.
60This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
61of FPGA-based solutions is limited by the lack of design flow automation. Nowadays, there are neither commercial
62nor academic  tools covering the whole design process.
63For instance, with SOPC Builder from Altera, users can select and parameterize IP components
64from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor
65and bus interface cores, as well as incorporate their own IP. Designers can then generate
66a synthesized netlist, simulation test bench and custom software library that reflect the hardware
67configuration.
68Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
69(Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
70simulate the platform at a high design level (systemC).
71In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
72tool to implement designs on Altera devices (Stratix, Arria, Cyclone).
73PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description.
74Nevertheless, they can only deal with data dominated applications and they do not handle the platform level.
75The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to
76Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs.
77Designers can design and simulate a system using MATLAB and Simulink. The tool will then
78automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx
79pre-optimized algorithms.
80However, this tool targets only DSP based algorithms.
81\\
82Consequently, designers developping an embedded system needs to master for example
83SoCLib for design exploration,
84SOPC Builder at the platform level,
85PICO for synthesizing the data dominated coprocessors
86and Quartus for design implementation.
87This requires an important tools interfacing effort and makes the design process very complex
88and achievable only by designers skilled in many domains.
89The aim of the COACH project is to integrate all these tools in the same framework and to allow \textbf{pure software} developpers to realize embedded systems.
90\par
91The combination of the framework dedicated to software developpers and FPGA target, allows to gain
92market share over Multi-core CPUs and GPUs HPC based solutions.
93Moreover, one can expect that small and even very small companies will be able to propose embedded
94system and accelerating solutions for standard software applications with acceptable prices, thanks
95 to the elimination of huge hardware investment in opposite to ASIC based solution.
96\\
97This new market may explode in the same way as the micro-computer market in the eighties. This success was due
98to the low cost of the first micro-processors (compared to main frames) and the advent of high level
99programming languages which allowed a high number of programmers to launch start-ups in software
100engineering.
101
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