source: anr/section-2.1.tex @ 97

Microelectronic components allow the integration of complicated functions into products, increases
commercial attractivity of these products and improves their competitivity.
Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
thanks to the developpment of design methodologies and tools for embedded systems.
\par
Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing
and manufacturing ASICs is very high.
An IC foundry costs several billions of euros and the fabrication of a specific circuit
costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
million USD.
Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium
volume markets.
\par
Today, FPGAs become important actors in the computational domain that was originally dominated
by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
on a per-application basis. For many applications, FPGAs offer significant performance benefits over
microprocessors implementation. There is still a performance degradation of one order
of magnitude versus an equivalent ASIC implementations, but low cost 
(500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive 
choice for low-to-medium volume applications. 
Since their introduction in the mid eighties, FPGAs evolved from a simple, 
low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that
provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, 
on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
complex systems like multi-processors platform with application dedicated coprocessors. 
Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
various application domains. 
This market is in significant expansion and is estimated to 914\,M\$ in 2012.

\begin{table}\leavevmode\center
\begin{tabular}{|l|l|l|l|}\hline
Segment         & 2010  & 2011  & 2012 \\\hline\hline
Communications  & 1,867 & 1,946 & 2,096 \\
High end        & 467   & 511   & 550 \\\hline
Consumer        & 550   & 592   & 672 \\
High end        & 53    & 62    & 75 \\\hline
Automotive      & 243   & 286   & 358 \\
High end        & -     & -     & - \\\hline
Industrial      & 1,102 & 1,228 & 1,406 \\
High end        & 177   & 188   & 207 \\\hline
Military/Aereo  & 566   & 636   & 717 \\
High end        & 56    & 65    & 82 \\\hline\hline
Total FPGA/PLD  & 4,659 & 5,015 & 5,583 \\
Total High-End  FPGA    & 753   & 826   & 914 \\\hline
\end{tabular}
\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
\end{table}
\par

This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions 
is limited by the lack of design flow automation. Nowadays, there are neither commercial 
nor academic  tools covering the whole design process from the system level specification to the bit stream
generation.
%For instance, with SOPC Builder from Altera, users can select and parameterize IP components 
%from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor 
%and bus interface cores, as well as incorporate their own IP. Designers can then generate 
%a synthesized netlist, simulation test bench and custom software library that reflect the hardware 
%configuration.
%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
(%Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
%simulate the platform at a high design level (systemC). 
%In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
%tool to implement designs on Altera devices (Stratix, Arria, Cyclone).
%PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description.
%Nevertheless, they can only deal with data dominated applications and they do not handle the platform level.
%The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to 
%Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. 
%Designers can design and simulate a system using MATLAB and Simulink. The tool will then 
%automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx 
%pre-optimized algorithms. 
%However, this tool targets only DSP based algorithms.

Consequently, a designer developping an embedded system needs to master
four different design environment : a virtual prototyping environment such as SoCLib for system level exploration,
an architecture compiler (such as SOPC Builder from Altera, or System generator from Xilinx) to define the
hardware architecture, one or several HLS tools (such as PICO [CITATION] ou CATAPULT [CITATION]) for 
coprocessor synthesis, and finally a backend synthesis tool (such as Quartus or YYYY) for the bit-stream generation.

The aim of the COACH project is to integrate all these design steps into a single design framework.
and to allow \textbf{pure software} developpers to develop embedded systems.
\par
We believe that the combination of a design environment dedicated to software developpers and the FPGA target, 
allows small and even very small companies to propose embedded system and accelerating solutions 
for standard software applications with acceptable prices.

This new market may explode in the same way as the micro-computer market in the eighties,
whose success was due to the low cost of the first micro-processors (compared to main frames) 
and the advent of high level programming languages which allowed a high number of programmers 
to launch start-ups in software engineering.