source: anr/section-2.2.tex @ 21

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1The aim of this project is to propose an open-source framework for
2architecture synthesis targeting mainly field programmable gate array
3circuits (FPGA).
4\\ % LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
5To evaluate the different architectures, the project uses the prototyping
6platform of the SoCLIB ANR project (2006-2009).
7\\ % LIEN AVEC AUTRES PROJETS: IRISA
8The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing
9joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
10extraction algorithms and datapath merging techniques to the synthesis of customized
11ASIP processors.
12\\
13On the HPC application side, we also hope to benefit from the experience in
14hardware acceleration of bioinformatic algorithms/workfows gathered by the
15CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
16be able to validate the framework on real-life HPC applications.
17\par
18%%% EXPERTISE DANS DES DOMAINES: LIP6/TIMA/LAB-STIC OK
19Regarding the expertise in  High Level Synthesis (HLS), the project
20leverages on know-how acquired over 15 years with GAUT~\cite{gaut08} project
21developped in Lab-STIC laboratory and UGH~\cite{ugh08} project developped
22in LIP6 and TIMA laboratories. \\
23Regarding architecture synthesis skills, the project is based on a know-how
24acquired over 10 years with the COSY European project (1998-2000) and the
25DISYDENT~\cite{disydent05} project developped in LIP6.\\
26%%% EXPERTISE DANS DES DOMAINES: IRISA OK
27Regarding Application Specific Instruction Processor (ASIP) design, the
28CAIRN group at INRIA Bretagne Atlantique benefits from several years of
29expertise in the domain of retargetable compiler
30(Armor/Calife\cite{FIXME:IRISA} since 1996, and the Gecos
31compilers\cite{FIXME:IRISA} since 2002).
32%%% EXPERTISE DANS DES DOMAINES: FIXME:LIP
33\mustbecompleted{For polyedric transformations and memory optimization, SYNTOL, BEE, ... LIP (CA ou PF)}
34\par
35%%% DESCRIPTION DES PROJETS ANR UTILISES: SOCLIB OK
36The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to
37describe hardware architectures with shared memory space and to deploy software
38applications on them to evaluate their performance.
39The heart of this platform is a library containing simulation models (in SystemC)
40of hardware IP cores such as processors, buses, networks, memories, IO controller.
41The platform provides also embedded operating systems and software/hardware
42communication components useful to implement applications quickly.
43However, the synthesisable description of IPs have to be provided by users. \\
44This project enhances SoCLib by providing synthesisable VHDL of standard IPs.
45In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable
46description of an IP (coprocessor) from a sequential algorithm.
47\par
48%%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes)
49%%% 2 IRISA ?
50%%% 2 ASIP tool such as ...
51%%% 2 ...
52%%% 2 Coach uses pattern extractions from ROMA
53\mustbecompleted{ROMA \\...\\...\\...\\...\\...\\...\\...\\IRISA (SD)\\}
54\par
55% FIXME A VERIFIER L'appel d'offre
56The different points proposed in this project cover priorities defined by the commission
57experts in the field of Information Technolgies Society (IST) for Embedded
58systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
59and allowing to apply efficiently applications and various products on embedded platforms,
60considering resources constraints (delais, power, memory, etc.), security and quality
61services$>>$.
62\\
63Our team aims at covering all the steps of the design flow of architecture synthesis.
64Our project overcomes the complexity of using various synthesis tools and description
65languages required today to design architectures.
66
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