source: anr/section-2.2.tex @ 70

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2% Relevance of the proposal
3
4The COACH proposal addresses directly the Embedded Systems of
5the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
6providing the industry the novel design capabilities enabling them to increase their
7design productivity with design exploration and synthesis methods that are placed on top
8of the state-of-the-art methods, and thus, allowing the industry to better cope with the
9complexity of designed digital systems.
10\par
11COACH will also contribute to the following strategic objectives of the ARPEGE program:
12COACH will specifically contribute to enable the building of open development and run-time
13environments for software and services, interoperable middleware and tools to support
14developers in the production of embedded software, through all phases of the software lifecycle,
15from requirements analysis until deployment and maintenance.
16\\
17More specifically, COACH focuses on:
18\begin{itemize}
19\item High level methods and concepts (esp. requirements and architectural level) for system
20design, development and integration, addressing complexity aspects and modularity.
21\item Open and modular development environments, enabling flexibility and extensibility by
22means of new or sector-specific tools and ensuring consistency and traceability along the
23development lifecycle.
24\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
25environment, suitable for co-operative and distributed development.
26\end{itemize}
27COACH outcome will contribute to strengthen Europe's competitive position by developing
28technologies and methodologies for product development, focusing (in compliance with the
29scope of the above program) on technologies, engineering methodologies, novel tools,
30methods which facilitate resource use efficiency. The approaches and tools to be developed
31in COACH will enable new and emerging information technologies for the development,
32manufacturing and integration of devices and related software into end-products.
33\\
34This project proposes an open-source framework for architecture synthesis targeting
35Field Programmable Gate Array circuits (FPGA).
36\par
37% LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
38To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009).
39\\ % LIEN AVEC AUTRES PROJETS: IRISA
40The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing
41joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
42extraction algorithms and datapath merging techniques to the synthesis of customized
43ASIP processors.
44\par
45On the HPC application side, we also hope to benefit from the experience in
46hardware acceleration of bioinformatic algorithms/workfows gathered by the
47CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
48be able to validate the framework on real-life HPC applications.
49\par
50%%% EXPERTISE DANS DES DOMAINES: LIP6/TIMA/LAB-STIC OK
51Regarding the expertise in  High Level Synthesis (HLS), the project
52leverages on know-how acquired over 15 years with GAUT~\cite{gaut08} project
53developped in Lab-STIC laboratory and UGH~\cite{ugh08} project developped
54in LIP6 and TIMA laboratories. \\
55Regarding architecture synthesis skills, the project is based on a know-how
56acquired over 10 years with the COSY European project (1998-2000) and the
57DISYDENT~\cite{disydent05} project developped in LIP6.\\
58%%% EXPERTISE DANS DES DOMAINES: IRISA OK
59Regarding Application Specific Instruction Processor (ASIP) design, the
60CAIRN group at INRIA Bretagne Atlantique benefits from several years of
61expertise in the domain of retargetable compiler
62(Armor/Calife\cite{FIXME:IRISA} since 1996, and the Gecos
63compilers\cite{FIXME:IRISA} since 2002).
64%%% EXPERTISE DANS DES DOMAINES: FIXME:LIP
65%%%\mustbecompleted{For polyedric transformations and memory optimization, SYNTOL, BEE, ... LIP (CA ou PF)}
66
67Compsys was founded in 2002 by several senior researchers with experience in
68high performance computing and automatic parallelization. They have been
69among the initiators of the polyhedral model, a theory which serve to
70unify many parallelism detection and exploitation techniques for regular
71programs. It is expected that the techniques developped by Compsys for
72parallelism detection, scheduling, process construction and memory management
73will be very useful as a first step for a high-level synthesis tool.
74
75\par
76%%% DESCRIPTION DES PROJETS ANR UTILISES: SOCLIB OK
77The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to
78describe hardware architectures with shared memory space and to deploy software
79applications on them to evaluate their performance.
80The heart of this platform is a library containing simulation models (in SystemC)
81of hardware IP cores such as processors, buses, networks, memories, IO controller.
82The platform provides also embedded operating systems and software/hardware
83communication components useful to implement applications quickly.
84However, the synthesisable description of IPs have to be provided by users. \\
85This project enhances SoCLib by providing synthesisable VHDL of standard IPs.
86In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable
87description of an IP (coprocessor) from a sequential algorithm.
88\par
89%%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes)
90%%% 2 IRISA ?
91%%% 2 ASIP tool such as ...
92%%% 2 ...
93%%% 2 Coach uses pattern extractions from ROMA
94\mustbecompleted{ROMA \\...\\...\\...\\...\\...\\...\\...\\IRISA (SD)\\}
95\par
96% FIXME A VERIFIER L'appel d'offre
97The different points proposed in this project cover priorities defined by the commission
98experts in the field of Information Technolgies Society (IST) for Embedded
99systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
100and allowing to apply efficiently applications and various products on embedded platforms,
101considering resources constraints (delais, power, memory, etc.), security and quality
102services$>>$.
103\\
104Our team aims at covering all the steps of the design flow of architecture synthesis.
105Our project overcomes the complexity of using various synthesis tools and description
106languages required today to design architectures.
107
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