% Relevance of the proposal 

The COACH proposal addresses directly the Embedded Systems of
the ARPEGE program, aiming at providing solutions to the societal/economical challenges by
providing the industry the novel design capabilities enabling them to increase their
design productivity with design exploration and synthesis methods that are placed on top 
of the stat-of-theart methods, and thus, allowing the industry to better cope with the 
complexity of designed digital systems.
\par
COACH will also contribute to the following strategic objectives of the ARPEGE program:
COACH will specifically contribute to enable the building of open development and run-time
environments for software and services, interoperable middleware and tools to support
developers in the production of embedded software, through all phases of the software lifecycle,
from requirements analysis until deployment and maintenance.
\\
More specifically, COACH focuses on:
\begin{itemize}
\item High level methods and concepts (esp. requirements and architectural level) for system
design, development and integration, addressing complexity aspects and modularity.
\item Open and modular development environments, enabling flexibility and extensibility by
means of new or sector-specific tools and ensuring consistency and traceability along the
development lifecycle.
\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
environment, suitable for co-operative and distributed development.
\end{itemize}
COACH outcome will contribute to strengthen Europe's competitive position by developing
technologies and methodologies for product development, focusing (in compliance with the
scope of the above program) on technologies, engineering methodologies, novel tools,
methods which facilitate resource use efficiency. The approaches and tools to be developed 
in COACH will enable new and emerging information technologies for the development,
manufacturing and integration of devices and related software into end-products.
\\
This project proposes an open-source framework for architecture synthesis targeting 
Field Programmable Gate Array circuits (FPGA).
\par
% LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009).
\\ % LIEN AVEC AUTRES PROJETS: IRISA
The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing 
joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
extraction algorithms and datapath merging techniques to the synthesis of customized 
ASIP processors.
\par
On the HPC application side, we also hope to benefit from the experience in
hardware acceleration of bioinformatic algorithms/workfows gathered by the
CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
be able to validate the framework on real-life HPC applications.
\par
%%% EXPERTISE DANS DES DOMAINES: LIP6/TIMA/LAB-STIC OK
Regarding the expertise in  High Level Synthesis (HLS), the project
leverages on know-how acquired over 15 years with GAUT~\cite{gaut08} project
developped in Lab-STIC laboratory and UGH~\cite{ugh08} project developped
in LIP6 and TIMA laboratories. \\
Regarding architecture synthesis skills, the project is based on a know-how
acquired over 10 years with the COSY European project (1998-2000) and the
DISYDENT~\cite{disydent05} project developped in LIP6.\\
%%% EXPERTISE DANS DES DOMAINES: IRISA OK
Regarding Application Specific Instruction Processor (ASIP) design, the
CAIRN group at INRIA Bretagne Atlantique benefits from several years of
expertise in the domain of retargetable compiler
(Armor/Calife\cite{FIXME:IRISA} since 1996, and the Gecos
compilers\cite{FIXME:IRISA} since 2002).
%%% EXPERTISE DANS DES DOMAINES: FIXME:LIP
\mustbecompleted{For polyedric transformations and memory optimization, SYNTOL, BEE, ... LIP (CA ou PF)}
\par
%%% DESCRIPTION DES PROJETS ANR UTILISES: SOCLIB OK
The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to
describe hardware architectures with shared memory space and to deploy software
applications on them to evaluate their performance. 
The heart of this platform is a library containing simulation models (in SystemC)
of hardware IP cores such as processors, buses, networks, memories, IO controller.
The platform provides also embedded operating systems and software/hardware
communication components useful to implement applications quickly.
However, the synthesisable description of IPs have to be provided by users. \\
This project enhances SoCLib by providing synthesisable VHDL of standard IPs.
In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable 
description of an IP (coprocessor) from a sequential algorithm.
\par
%%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes)
%%% 2 IRISA ?
%%% 2 ASIP tool such as ... 
%%% 2 ...
%%% 2 Coach uses pattern extractions from ROMA
\mustbecompleted{ROMA \\...\\...\\...\\...\\...\\...\\...\\IRISA (SD)\\}
\par
% FIXME A VERIFIER L'appel d'offre
The different points proposed in this project cover priorities defined by the commission 
experts in the field of Information Technolgies Society (IST) for Embedded
systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
and allowing to apply efficiently applications and various products on embedded platforms,
considering resources constraints (delais, power, memory, etc.), security and quality
services$>>$.
\\
Our team aims at covering all the steps of the design flow of architecture synthesis.
Our project overcomes the complexity of using various synthesis tools and description 
languages required today to design architectures.