source: anr/section-2.2.tex @ 188

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2% Relevance of the proposal
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7The COACH proposal addresses directly the \emph{Embedded Systems} item of
8the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
9providing SMEs novel design capabilities enabling them to increase their
10design productivity with design exploration and synthesis methods that are placed on top
11of the state-of-the-art methods.
12This project proposes an open-source framework for mapping multi-tasks software applications
13on Field Programmable Gate Array circuits (FPGA).
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16COACH will contribute to build an open development and run-time
17environment, including communication middleware and tools to support
18developers in the production of embedded software, through all phases of the software lifecycle,
19from requirements analysis downto deployment and maintenance.
20More specifically, COACH focuses on:
21\begin{itemize}
22\item High level methods and concepts (esp. requirements and architectural level) for system
23design, development and integration, addressing complexity aspects and modularity.
24\item Open and modular development environments, enabling flexibility and extensibility by
25means of new or sector-specific tools and ensuring consistency and traceability along the
26development lifecycle.
27\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
28environment, suitable for co-operative and distributed development.
29\end{itemize}
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32COACH outcome will contribute to strengthen Europe's competitive position by developing
33technologies and methodologies for product development, focusing (in compliance with the
34scope of the above program) on technologies, engineering methodologies, novel tools,
35methods which facilitate resource use efficiency. The approaches and tools to be developed
36in COACH will enable new and emerging information technologies for the development,
37manufacturing and integration of devices and related software into end-products.
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39\parlf
40The COACH project will benefit from a number of previous recent projects:
41\begin{description}
42  \item[SOCLIB]
43    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories
44    (TIMA, LIP6, Lab-STICC, IRISA, ENST, Gipsa-Lab, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6
45        industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept).
46    It supports system level virtual prototyping of shared memory, multi-processors
47    architectures, and provides tools to map multi-tasks software application on these
48    architectures, for reliable performance evaluation.
49    The core of this platform is a library of SystemC simulation models for
50    general purpose IP cores such as processors, buses, networks, memories, IO controller.
51    The platform provides also embedded operating systems and software/hardware
52    communication middleware.
53    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
54    this project enhances SoCLib by providing the synthesisable VHDL models required
55    for FPGA synthesis.
56  \item[ROMA] The ROMA ANR project (http://roma.irisa.fr, 2007-2010)
57    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
58    proposes to develop a reconfigurable processor, exhibiting high
59    silicon density and power efficiency, able to adapt its computing
60    structure to computation patterns that can be speed-up and/or
61    power efficient.  The ROMA project study a pipeline-based of
62    evolved low-power coarse grain reconfigurable operators to avoid
63    traditional overhead, in reconfigurable devices, related to the
64    interconnection network.  The project will borrow from the ROMA
65    ANR project and the ongoing joint INRIA-STMicro
66    Nano2012 project to adapt existing pattern extraction algorithms
67    and datapath merging techniques to the synthesis of customized
68    ASIP processors.
69  \item[TSAR]
70    The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a
71    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
72    plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
73    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
74  \item[BioWic]
75    On the HPC application side, we also hope to benefit from the experience in
76    hardware acceleration of bioinformatic algorithms/workfows gathered by the
77    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
78    be able to validate the framework on real-life HPC applications.
79\end{description}
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82The laboratories involved in the COACH project have a well estabished expertise
83in the following domains:
84\begin{itemize}
85  \item 
86    In the field of High Level Synthesis (HLS), the project
87    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
88    developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
89    by the \upmc and \tima laboratories.
90  \item
91    Regarding system level architecture, the project is based on the know-how
92    acquired by the \upmc and \tima laboratories in the framework of various projects 
93    in the field of communication architectures for shared memory multi-processors systems
94    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
95    As an example, the DSPIN project is now used in the TSAR project.
96  \item
97    Regarding Application Specific Instruction Processor (ASIP) design, the
98    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
99    expertise in the domain of retargetable compiler
100    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
101    compilers~\cite{ASAP05} since 2002).
102\item
103    In the field of compilers, the Compsys group was founded in 2002
104    by several senior researchers with experience in
105    high performance computing and automatic parallelization. They have been
106    among the initiators of the polyhedral model, a theory which serve to
107    unify many parallelism detection and exploitation techniques for regular
108    programs. It is expected that the techniques developped by Compsys for
109    parallelism detection, scheduling, process construction and memory management
110    will be very useful as a front-end for the a high-level synthesis tools.
111\end{itemize}
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115The COACH project answers to several of the challenges found in different axis of the
116call for proposals. Keywords of the call are indicated below in italic writing.
117
118Axis 1 "Architectures des syst\`{e}mes embarqu\'{e}s" :
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120COACH will address new embedded systems architectures by allowing the design of
121Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
122constraints and objectives (real-time, low-power). It will permit to design  complex SoC
123based on IP cores (memory, peripherals, network controllers, communication processors),
124running Embedded Software, as well as an Operating System with associated middleware and
125API and using hardware accelerator automatically generated. It will also permit to use
126efficiently different dynamic system management techniques and re-configuration mechanisms.
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128Axis 2 "Infrastructures pour l'Internet, le calcul intensif ou les services" :
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130COACH will address High-Performance Computing (HPC) by helping designer to accelerate an
131application running on a PC by migrating critical parts into a SoC implemented on an FPGA
132plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer
133effort through the development of tools that translate high level language programs to FPGA
134configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance
135as well as reducing the required area.
136
137Axis 3 "Robotique et controle/commande" :
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139COACH will permit to design complex digital systems based on high-performance multi-core systems.
140Like in the consumer electronics domain (telecommunication, multimedia), future control applications
141will employ more and more SoC not just for typical consumer functionality, but also for safety and
142security applications (by performing complex analyses on data gathered with intelligent sensors,
143by initiating appropriate responses to dangerous phenomena...). Application domains for such systems
144are for example the automotive domain, as well as the aerospace and avionics domains (i.e. sophisticated on-board
145radar systems, collision-detection, intelligent navigation...).
146Manufacturing technology will also increasingly need high-end vision analysis and high-speed
147robot control. In all cases, high performance and real time requirements are combined with
148requirements to low power, low temperature, high dependability, and low cost.
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150Axis 5 "S\'{e}curit\'{e} et suret\'{e}" :
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152The results of the COACH project will help users to build cryptographic secure systems implemented in
153hardware or both in software/ hardware in an effective way, substantially enhancing the
154process productivity of the cryptographic algorithms hardware synthesis, improving the
155quality and reducing the design time and the cost of synthesised cryptographic devices.
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157COACH technologies can be used in both large and small business, as they will permit users to design
158embedded systems which meet a wide range of requirements: from low cost and low power consuming
159devices to very high speed devices, based on parallel computing. For enterprises that will use embedded
160systems designed via the approaches and tools targeted by COACH, there is the potential for greater
161efficiency, improved business processes and models. The net results: lower costs, faster response times,
162better service, and higher revenue.
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165\parlf
166Finally, it is worth to note that this project covers priorities defined by the commission
167experts in the field of Information Technolgies Society (IST) for Embedded
168Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
169and allowing to apply efficiently applications and various products on embedded platforms,
170considering resources constraints (delais, power, memory, etc.), security and quality
171services$>>$.
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