[97] | 1 | The first objective of COACH is to provide SMEs (Small and Medium Enterprises) an open-source framework to |
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| 2 | design embedded system on FPGA devices. |
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[30] | 3 | |
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[97] | 4 | Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) |
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| 5 | is not an option for most SMEs. Fortunately, the new FPGA (Field Programmable Gate Array) components, |
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| 6 | such as the Virtex5 family from Xilinx, or the Stratix4 family from Altera can implement a complete |
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| 7 | multi-processor architecture on a single chip. |
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| 8 | |
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| 9 | %But the design of a SoC (System on Chip) or MPSoC (Multi-Processor System on Chip) is a complex |
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| 10 | %task, requiring adequate design methods to efficiently model, explore, and analyze the |
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| 11 | %interactions between the software application and the hardware architectures. Moreover, most SMEs do not have |
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| 12 | %in-home expertise in the field of hardware design or VHDL/Verilog modeling. |
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| 13 | %In order to meet the increasing performance requirements, to decrease the development cost, and to |
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| 14 | %shorten the time-to-market, they need new design methodologies. |
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| 15 | |
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| 16 | %Current design methodologies provide quite low-level abstraction capabilities, and |
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| 17 | %there is an urgent need to leverage system level exploration through the use of a high-level |
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| 18 | %specification of the application and design space exploration tools. |
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| 19 | |
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| 20 | %The first system oriented approaches are appearing, among which those |
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| 21 | %based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs. |
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| 22 | |
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| 23 | The COACH project will leverage on the expertise gained in the field of virtual prototyping |
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| 24 | with the SoCLib platform, to propose a new design flow based on a small number of architectural templates. |
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| 25 | An architectural template is a generic, parametrized architecture, relying on a predefined library |
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| 26 | of IP cores. |
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| 27 | Besides using a specific collection of general purpose IP cores (such as processors cores, |
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| 28 | embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural |
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| 29 | template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools. |
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| 30 | During this project, the COACH partners will develop three different architectural templates: |
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| 31 | |
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| 32 | \begin{enumerate} |
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| 33 | \item An \altera architectural template based on the \altera IP core library and the AVALON system bus. |
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| 34 | \item A \xilinx architectural template based on the Xlinx IP core library and the OPB system bus. |
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| 35 | \item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure. |
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| 36 | \end{enumerate} |
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| 37 | |
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| 38 | The proposed design flow starts from a high level description of the application, specified as a set of |
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| 39 | parallel tasks written in C, without any assumption on the hardware or software implementation |
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| 40 | of these tasks. It let the system |
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| 41 | designer in charge of expessing the coarse grain parallelism of the application, gives the designer |
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| 42 | the possibility to explore various mapping of the application on the selected template architecture, |
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| 43 | and offers a high predictability of results with respect to cost and performance objectives. |
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| 44 | |
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| 45 | When this interactive, system level, design space exploration is completed (converging to |
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| 46 | a specific mapping on a specific version of the selected architectural template), the rest of the flow |
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| 47 | is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary |
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| 48 | code for the software running on the embedded processors, and the bit-stream to program the the target FPGA |
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| 49 | will be automatically generated by the COACH tools. |
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| 50 | |
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[17] | 51 | \par |
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[97] | 52 | The strength of the COACH approach is the strong integration of the high-level synthesis tools |
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| 53 | in a plat-form based design flow supporting virtual prototyping and design space exploration. |
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| 54 | Most building blocks already exist (resulting from previous projects): the GAUT |
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| 55 | or UGH synthesis tools, the MutekH or DNA embedded operating systems, the ASIP technology, |
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| 56 | the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool, |
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| 57 | as well as the SoCLib library of systemC simulation models. They must now be integrated in |
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| 58 | a consistent design flow. |
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| 59 | %The five academic laboratories worked very closely during more than one year (one monthly meeting |
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| 60 | %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating |
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| 61 | %those various technologies, and to define the detailed architecture of the proposed design flow. |
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| 62 | \par |
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[17] | 63 | |
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[97] | 64 | In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks |
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| 65 | have been previously developed by academic laboratories. |
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| 66 | |
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| 67 | |
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| 68 | %Finally, the key points of the proposed design flow are : |
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| 69 | %\begin{itemize} |
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| 70 | %\item |
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| 71 | %\textbf{System level exploration}: The application coarse grain parallelism |
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| 72 | %is explicitely described as a Tasks and Communication Graph (TCG). |
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| 73 | %A template architecture is selected, and the performances are evaluated |
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| 74 | %on various variant of this architecture using the SoCLib virtual protyping |
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| 75 | %environment. This result in a specific hardware/software partitioning. |
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| 76 | %This system level exploration is fully controlled by the system designer, and is driven |
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| 77 | %by cost, throughput, latency and power consumption criteria. |
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| 78 | % |
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| 79 | %\item |
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| 80 | %\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been |
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| 81 | %identified as mandatory, they will be generated by the high level synthesis (HLS) tools. |
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| 82 | %The Coach framework will integrate various HLS tools, supporting the micro-architectural space |
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| 83 | %design exploration. Here again, the exploration criteria are cost, throughput, latency |
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| 84 | %and power consumption. |
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| 85 | %At this stage, preliminary source-level transformations and optimisations by front-end |
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| 86 | %tools will be required to improve the efficiency of the back-end HLS tools. |
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| 87 | % |
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| 88 | %\item |
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| 89 | %\textbf{Early performance evaluation}: For each point in the design space, |
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| 90 | %figures of merit must be available such as throughput, latency, power |
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| 91 | %consumption, area, memory allocation and data locality. They are evaluated |
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| 92 | %by reliable estimators obtained by running the actual multi-task software |
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| 93 | %application on the virtual prototype. |
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| 94 | % |
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| 95 | %\item |
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| 96 | %\textbf{Independance from the Target FPGA}: The COACH description of the system |
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| 97 | %(both hardware and software) should be independent of the FPGA family. |
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| 98 | %Every point of the design space can be implemented on any FPGA component, |
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| 99 | %as long as it contains the hardware ressources required by the selected architectural template. |
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| 100 | %Basically, COACH will support both Altera and Xilinx FPGA families. |
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| 101 | %\end{itemize} |
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| 102 | % |
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| 103 | |
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| 104 | |
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| 105 | |
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