source: anr/section-2.tex @ 25

The emerging complex and integrated heterogeneous embedded system platforms require
adequate design methods able to efficiently model, explore, analyze and design the ever complex SW
and HW architectures. Future Embedded Systems suppliers, in order to meet rapidly increasing
performance requirements linked with a pressure to lower development cost and shorten time-tomarket,
will have to adopt new design methods and flows able to keep pace with the increasing
complexity of design problems. Such methods, addressing these challenges starting from high levels of
abstraction, will have to perform large solution space exploration jointly for SW and HW (possibly
reconfigurable), involving almost marginal design effort and offering a high predictability of results
with respect to cost- and performance-functions.
Current design methodologies provide quite low-level abstraction capabilities. However in a few years
from now tens of programmable processors will be embedded in an IC with together over 100M
transistors adding to the complexity of the problem of architecting such systems. Taking into account
that the complexity of the SW part is pacing up at an even faster speed, current solutions to perform
design space exploration, mainly manually based, by no means do supply a performance of adequate
sufficiency.
Consequently, there is an urgent need to leverage system level
exploration through the use of a high level specification of the application and an early design
space exploration steps. The first system oriented approaches are appearing, among which those
based on C/C++ and SystemC are most popular. Such approaches can take place before and/or after
the co-design or architecture refinement steps and targets the design space pruning in order to fully
exploit potential solutions that meet design and application constraints (power, latency,
throughput) within the design and market timeframe.
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Thus, new system-level design flows need to be developed, enabling the exploration of an application
independently of the implementation, this almost at the beginning of the design process. A
fundamental element of this evolution is the definition of abstraction layers that should allow the
systematic re-use of SW and HW components at the system level driven by performance estimation
and analysis. It is the context in which the COACH modeling and estimation methods combined with 
compilers and design space exploration techniques. This approach will cause a real breakthrough in 
the embedded system design methodology, i.e. one of the radical innovations.
\\
The reason is that COACH precedes the use of high-level design tools in the embedded
systems design flows. In that way, it will make possible a real and efficiently combined
exploitation of high-level synthesis tools, parallelising approaches and compilers, already
available on the market. These tools and approaches are not yet massively adopted, precisely
because this decisive design step is missing. COACH will indeed permit (i) to predict and
control implementation optimizations, (ii) to target multiple implementation technologies
(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
and low-level design tools in a unique seamless design flow.
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The performance estimation methods combined with the design space exploration techniques will
finally allow the design process to start from system level specification and automatically explore the
potential architectures in order to find out the optimal implementation in a shorter design time and at
a lower global cost.
\par
To get an efficient embedded system, designer has to take into account
application characteristics when it chooses one of the former technologies.
This choice is not easy and in most cases designer has to try different
technologies to retain the most adapted one.
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The first objective of COACH is to provide an open-source framework to
design embedded system on FPGA device.
COACH framework allows designer to explore various software/hardware
partitions of the target application, to run timing and functional
simulations and to generate automatically both the software and the
synthesizable description of the hardware.
The main topics of the project are:
\begin{itemize} 
\item
Design space exploration: It consists in analysing the application runnig
on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
hardware/software partitioning of tasks depending on technology choice.
This exploration is driven basically by throughput, latency and power
consumption criteria.
\item
Micro-architectural exploration: When hardware components are required, the
HLS tools of the framework generate them automatically. At this stage the
framework provides various HLS tools allowing the micro-architectural space
design exploration. The exploration criteria are also throughput, latency
and power consumption.
%FIXME:CA
%FIXME:CA At this stage, preliminary source-level transformations will be
%FIXME:CA required to improve the efficiency of the target component.
%FIXME:CA COACH will also provide such facilities, such as automatic parallelization
%FIXME:CA and memory optimisation.
\item
Performance measurement: For each point of design space exploration,
metrics of criteria are available such as throughput, latency, power
consumption, area, memory allocation and data locality. They are evaluated
using virtual prototyping, estimation or analysing methodologies.
\item
Targeted hardware technology: The COACH description of system is
independent of the FPGA family.  Every point of the design exploration
space can be implemented on any FPGA having the required resources.
Basically, COACH handles both Altera and Xilinx FPGA families.
\end{itemize}
As an extension of embedded system design, COACH deals also with High
Performance Computing (HPC).
In HPC, the kind of targeted application is an existing one running on PC.
COACH helps designer to accelerate it by migrating critical parts into a
SoC implemented on a FPGA plugged to the PC bus.
\par
COACH is the result of the will of several laboratory to unify their know
how and skills in the following domains: Operating system and hardware
communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
HLS (LIP6, Lab-STIC and LIP).
The project objective is to integrate these various domains into a unique
free framework (licence ...) masking as much as possible these domains and
its different tools to the user.