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1% les objectifs scientifiques/techniques du projet.
2The objectives of the COACH project are to develop a complete framework to HPC
3(accelerating solutions for existing software applications) and embedded
4applications (implementing an application on a low power standalone
5device).  The design steps are presented figure~\ref{coach-flow}.
6\begin{figure}[hbtp]\leavevmode\center
7  \includegraphics[width=.8\linewidth]{flow}
8  \caption{\label{coach-flow} COACH design flow}
9\end{figure}
10\begin{description}
11\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
12which remains on a PC and the SoC application which is mapped on the FPGA.
13COACH will allow to automatically translate high level language programs to FPGA configurations.
14In addition, it will provide a SystemC simulation model of the whole system (PC+communication+FPGA-SoC)
15which will allow performance evaluation of the partitioning.
16\item[SoC design:] In this phase,
17COACH will allow the user to obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description. 
18This description will consist of a process network corresponding to the application,
19an OS, an instance of a generic hardware platform
20and a mapping of processes on the platform components. COACH will offer different targets to map the processes: 
21software (the process runs on a SoC processor),
22ASIP (the process runs on a SoC processor enhanced with dedicated instructions),
23and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus).
24\item[Application compilation:] Once the SoC description is validated through performances analysis, COACH will generate automatically
25an FPGA bitstream containing the hardware platform with the SoC application software and
26an executable containing the host application. The user will be able to launch the application by
27loading the bitstream on an FPGA and running the executable on PC.
28\end{description}
29 
30% l'avancee scientifique attendue. Preciser l'originalite et le caractere
31% ambitieux du projet.
32%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}
33
34%The main scientific contribution of the project is to unify various synthesis techniques
35%(same input and output formats) allowing the user to swap without engineering effort
36%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
37%Another advantage of this framework is to provide different abstraction levels from
38%a single description.
39%Finally, this description is device family independent and its hardware implementation
40%is automatically generated.
41
42% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
43System design is a very complex task and in this project we will try to simplify it
44as much as possible. For this purpose the following scientific and technological barriers
45have to be addressed.
46        \\
47        \\
48%\begin{description}
49%\item[]
50\textit{Design Space Exploration:}\\
51    The COACH environment will allow to easily map an application described by using a process
52        network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will
53        permit to explore the design space by allowing system designer to select and
54        parameterize the target architecture, and to define the best hardware/software
55        partitioning of the application.
56        \\
57        \\
58%\item[High-Level Synthesis:]
59\textit{High-Level Synthesis:}\\
60    COACH will allow the automatic generation of hardware accelerators when required
61        by using High-Level Synthesis (HLS) tools.
62        HLS will thus be fully integrated into a complete system-level design environment.
63        Moreover, COACH will support both data and control dominated applications.
64    Indeed, the HLS tools of COACH will support a common language and coding style
65        to avoid re-engineering by the designer.
66    COACH will provide a tool which will automatically explore the micro-architectural
67        design space of coprocessor.
68\\
69        \\
70%\item[High-level code transformation:]
71\textit{High-level code transformation:}\\ 
72    COACH will allow to optimize the memory usage, to enhance the parallelism through
73        loop transformations and parallelization. The challenge is to identify the coarse
74        grained parallelism and to generate,
75        from a sequential algorithm, application containing multiple communicating
76        tasks. To this aim, one may adapt techniques which were developed in the 1990 for
77        the construction of distributed programs. However, in the context of HLS, there are
78        still several original problems to be solved, mainly to do with the construction of
79        FIFO communication channels and with memory optimization.
80        Additionnal preprocessing, source-level transformations, are thus
81        required to improve the process.
82        Particularly, this includes parallelism exposure and efficient memory mapping.
83        COACH will support code transformation by providing a source to source C2C tool.
84\\
85        \\
86%\item[Platform based design:]
87\textit{Platform based design: }\\
88    COACH will define architectural templates that can be customized by adding
89    dedicated coprocessors and ASIPs and by fixing template parameters such as
90    the number of embedded processors, the number of sizes of embedded memory banks
91    or the embedded the operating system.
92    However, the specification of the application will be independant of both the
93    architectural template and the target FPGA device.
94\\
95        \\
96%\item[Hardware/Software communication middleware:]
97\textit{Hardware/Software communication middleware: }\\
98    COACH will implement an homogeneous HW/SW communication infrastructure and
99    communication APIs (Application Programming Interface), that will be used for
100    communications between software tasks running on embedded processors and
101    dedicated hardware coprocessors. This will allow explore the design space by
102        mapping the tasks of the application (described as a process network) on a
103        shared-memory, MPSoC architecture.
104\\
105        \\
106%\item[Processor customization:]
107\textit{Processor customization: }\\
108ASIP design will be addressed by the COACH project. COACH will allow system designers to explore
109the various level of interactions between the original CPU micro-architecture and its
110  extension. It will also allow to retarget the compiler instruction-selection pass. Finally,
111 COACH will integrate ASIP design in a complete System-level design framework.
112\\
113        \\
114%\item [High-Performance Computing:] The main problem in HPC is the communication
115\textit{High-Performance Computing: }\\
116The main problem in HPC is the communication
117between the PC and the SoC. This problem has 2 aspects. The first one is the run-time
118efficiency. The second is its engineering  cost, especially if one want to refine an
119implementation at several abstract levels.
120COACH will help designer to accelerate applications by migrating critical parts into a
121SoC embedded into an FPGA device plugged to the PC PCI/X bus.
122\\
123%\item The COACH design flow has a top-down approach. In such a case,
124%the required performance of a coprocessor (clock frequency, maximum cycles for
125%a given computation, power consumption, etc) are imposed by the other system
126%components. The challenge is to allow the user to control accurately the synthesis
127%process. For instance, the clock frequency must not be a result of the RTL synthesis
128%but a strict synthesis constraint.
129
130%\end{description}
131
132%Presenter les resultats escomptes en proposant si possible des criteres de reussite
133%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en
134%fin de projet.
135The main result is the framework. It is composed concretely of:
136a communication middleware for HPC,
1375 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
138Memory optimisation HLS and ASIP),
1393 architectural templates that are synthesizable and that can be prototyped,
140one design space exploration tool,
1412 operating systems (DNA/OS and MUTEKH).
142\\
143The framework fonctionality will be demonstrated with the demonstrators
144(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
145page~\ref{subtask-tutorial}).
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