source: anr/section-3.2.tex @ 18

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1% les objectifs scientifiques/techniques du projet.
2The objectives of COACH project are to develop a complete framework to
3HPC (accelerating solutions for existing software applications)
4and embedded applications (implementing an application on a low power standalone device).
5The design steps are presented figure 1.
6\begin{figure}[hbtp]\leavevmode\center
7  \includegraphics[width=.8\linewidth]{flow}
8  \caption{\label{coach-flow} COACH flow.}
9\end{figure}
10\begin{description}
11\item[HPC setup] Here the user splits the application into 2 parts: the host application
12which remains on PC and the SoC application which migrates on SoC.
13The framework provides a simulation model allowing to evaluate the partitioning.
14\item[SoC design] In this phase,
15The user can obtain simulators at different abstraction levels of the SoC by giving to COACH framework
16a SoC description. 
17This description consists of a process network corresponding to the SoC application,
18an OS, an instance of a generic hardware platform
19and a mapping of processes on the platform components. The supported mapping are
20software (the process runs on a SoC processor),
21XXXpeci (the process runs on a SoC processor enhanced with dedicated instructions),
22and hardware (the process runs into a coprocessor generated by HLS and plugged on the SoC bus).
23\item[Application compilation] Once SoC description is validated, COACH generates automatically
24an FPGA bitstream containing the hardware platform with SoC application software and
25an executable containing the host application. The user can launch the application by
26loading the bitstream on FPGA and running the executable on PC.
27\end{description}
28 
29% l'avancee scientifique attendue. Preciser l'originalite et le caractere
30% ambitieux du projet.
31The main scientific contribution of the project is to unify various synthesis techniques
32(same input and output formats) allowing the user to swap without engineering effort
33from one to an other and even to chain them, for example, to run polyedric transformation
34before synthesis.
35Another advantage of this framework is to provide different abstraction levels from
36a single description.
37Finally, this description is device family independent and its hardware implementation
38is automatically generated.
39
40% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
41System design is a very complicated task and in this project we try to simplify it
42as much as possible. For this purpose we have to deal with the following scientific
43and technological barriers.
44\begin{itemize}
45\item The main problem in HPC is the communication between the PC and the SoC.
46This problem has 2 aspects. The first one is the efficiency. The second is to
47eliminate enginnering effort to implement it at different abstract levels.
48\item COACH design flow has a top-down approach. In the such case,
49the required performance of a coprocessor (run frequency, maximum cycles for
50a given computation, power consumption, etc) are imposed by the other system
51components. The challenge is to allow user to control accurately the synthesis
52process. For instance, the run frequency must not be a result of the RTL synthesis
53but a strict synthesis constraint.
54\item HLS tools are sensitive to the style in which the algorithm is written.
55In addition, they are are not integrated into an architecture and system
56exploration tool.
57Consequently, engineering work is required to swap from a tool to another,
58to integrate the resulting simulation model to an architectural exploration tool
59and to synthesize the generated RTL description.
60%CA Additionnal preprocessing, source-level transformations, are thus
61%CA required to improve the process.
62%CA Particularly, this includes parallelism exposure and efficient memory mapping.
63\item Most HLS tools translate a sequential algorithm into a coprocessor
64containing a single data-path and finite state machine (FSM). In this way,
65only the fine grained parallelism is exploited (ILP parallelism).
66The challenge is to identify the coarse grained parallelism and to generate,
67from a sequential algorithm, coprocessor containing multiple communicating
68tasks (data-paths and FSMs).
69\end{itemize}
70
71%Presenter les resultats escomptes en proposant si possible des criteres de reussite
72%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en
73%fin de projet.
74The main result is the framework. It is composed concretely of:
752 HPC communication shemes with their implementation,
765 HLS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
77Memory optimisation HLS and ASIP),
783 systemC based virtual prototyping environment extended with synthesizable
79RTL IP cores (generic, ALTERA/NIOS/AVALON, XILINX/MICROBLAZE/OPB),
80one design space exploration tool,
81one operating system (OS).
82\\
83The framework fonctionality will be demonstrated with XXX-EXAMPLE1, XXX-EXAMPLE2
84and XXX-EXAMPLE3 on 4 archictures (generic/XILINX, generic/ALTERA,
85proprietary/XILINX, proprietary/ALTERA).
86
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