[12] | 1 | \begin{figure}\leavevmode\center |
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| 2 | \includegraphics[width=.8\linewidth]{architecture-csg} |
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| 3 | \caption{\label{archi-csg} software architecture for embedded system generation} |
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| 4 | %\end{figure}\begin{figure}\leavevmode\center |
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| 5 | \mbox{}\vspace*{1ex}\\ |
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| 6 | \includegraphics[width=.8\linewidth]{architecture-hls} |
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| 7 | \caption{\label{archi-hls} software architecture of HLS} |
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| 8 | %\end{figure}\begin{figure}\leavevmode\center |
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| 9 | \mbox{}\vspace*{1ex}\\ |
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| 10 | \includegraphics[width=.8\linewidth]{architecture-hpc} |
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| 11 | \caption{\label{archi-hpc} software architecture of HPC} |
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| 12 | \end{figure} |
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| 13 | % |
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| 14 | The figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} |
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| 15 | summarize the software architecture of COACH framework we plan to develop. |
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| 16 | In figures, the dotted boxes are the softwares or formats that COACH |
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| 17 | has to provide or define. |
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| 18 | \vspace*{.75ex}\par |
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| 19 | For the system genration presented figure~\ref{archi-csg}, the conductor is |
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| 20 | the program \verb!CSG! (COACH System Generator). Its inputs are a process |
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| 21 | network and miscellaneaous generation parameters. |
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| 22 | The main parameters are the template of the target hardware architecture |
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| 23 | with its instanciation parameters, the hardware/software mapping of the |
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| 24 | tasks and the FPGA device. |
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| 25 | From these inputs \verb!CSG! can generate the system (software \& hardware) as |
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| 26 | a SystemC simulator to prototype and explore quickly the system design |
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| 27 | space and/or as a bitstream directly downloadable on the FPGA device. |
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| 28 | For processing, \verb+CSG+ requires 1) a hardware template found into the |
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| 29 | architecture library, 2) a micro-kernel, it chooses among |
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| 30 | two in the micro kernel library, 3) the system hardware components that |
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| 31 | are taken from the SystemC model library for the simulator and from the |
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| 32 | VHDL component library for the FPGA bitstream. |
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| 33 | For generating the coprocessor of a task mapped as harware, \verb+CSG+ |
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| 34 | controls the HLS tools described below. |
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| 35 | \\ |
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| 36 | To proove CSG that COACH is open and CSG is really configurable, COACH will |
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| 37 | basically support 3 architecture template (the COACH template based on a |
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| 38 | MIPS processors and a VCI token ring, the Altera template based on the NIOS |
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| 39 | and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus) |
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| 40 | and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced |
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| 41 | by the \mustbecompleted{FIXME:zied} contribution that consists in |
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| 42 | implementing an other hardware target. |
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| 43 | \\ |
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| 44 | Finally, it is important to notice that this work is a strong |
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| 45 | enhancement of the SocLib software. |
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| 46 | \vspace*{.75ex}\par |
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| 47 | The software architecture for HLS is presented figure~\ref{archi-hls}. |
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| 48 | The input is a task of the process network. The HLS tools do not work |
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| 49 | directly on the C++ task description but on an internal format called |
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| 50 | \xcoach generated by a the GNU C compiler (GCC) tainted by a COACH |
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| 51 | driver. This allows on the one hand to insure that all the tools will |
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| 52 | accept the same C++ description and on the other hand to make possible |
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| 53 | to chain them. The front-end tools read a \xcoach description and writes |
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| 54 | a new \xcoach description that exibits possible parallelism or implement |
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| 55 | specific instruction for ASIP. The back-end tools read a \xcoach |
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| 56 | description and generates a \xcoach+ description that is a \xcoach |
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| 57 | description anotated with hardware information to let work the VHDL systemC |
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| 58 | drivers. Furthermore, the back-end tools uses a macro-cell library. |
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| 59 | \vspace*{.75ex}\par |
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| 60 | The software architecture for HPC is presented figure~\ref{archi-hpc}. |
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| 61 | \mustbecompleted{FIXME Miss HPC description\\\ldots\\\ldots\\\ldots\\\ldots.} |
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| 62 | \vspace*{.75ex}\par |
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| 63 | The project is splitted into 8 tasks numbered from 0 to 7. |
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| 64 | The first task (task 0) is the project management, the last one (task 7) is |
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| 65 | the dissemination the other task are listed below: |
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| 66 | \begin{enumerate} |
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| 67 | \item\textbf{\backbone:} This task groups the critical issues of the |
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| 68 | project. They consist of the definition of COACH inputs, the \xcoach |
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| 69 | format that is mandatory to develop the HLS tools and the HLS drivers |
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| 70 | that are mandatory for testing the HLS tools. |
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| 71 | \item\textbf{system generation:} This task groups \verb+CSG+s and the components |
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| 72 | required to generate the system simulator and bitstream except the HLS |
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| 73 | tools that belong to the task 3 and 4. These components are the |
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| 74 | operating systems, the VHDL description and SystemC models of the |
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| 75 | target hardware achitectures. |
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| 76 | \item\textbf{HLS front-end:} This task groups the 4 HLS front-head. Those |
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| 77 | are a tool that exhibits fine grain parallelism using polyedric |
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| 78 | transformation, a tool that exhibits coarse grain parallelism, |
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| 79 | a tool that minimizes the memory usage and a tool that implement ASIP. |
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| 80 | \item\textbf{HLS back-end:} This task groups two HLS back-end tool, one |
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| 81 | for treating the data oriented description, the second for treating the |
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| 82 | control dominated description. This task contains also a the |
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| 83 | development of a frequency adaptator that will allow the coprocessor |
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| 84 | to respect the processor \& bus frequency. |
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| 85 | \item\textbf{Communication software PC/FPGA-SoC:} This task groups all what is mandatorythe critical issues of the |
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| 86 | \item\textbf{Demonstrator:} This task groups the demostrators of the COACH project. |
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| 87 | \end{enumerate} |
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| 88 | This task division offers the avantage that tasks except for the "\backbone" and |
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| 89 | "demonstrator" task are almost independent at the development level as shown |
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| 90 | figure~\ref{dependence-dev}. The dependence at the validation level is |
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| 91 | presented figure~\ref{dependence-test}. It is more critical but the |
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| 92 | redundance in the tasks "HLS front-end", "HLS back-end" and "demonstrators" |
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| 93 | reduces this inter-dependence.\\ |
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| 94 | So if the first phasis of "\backbone" task is sucessfully conduced, most of the |
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| 95 | projet delivrables will be carry through, even if some delivrable are lated |
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| 96 | or missing. |
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| 97 | \begin{figure}\leavevmode\center |
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| 98 | \begin{minipage}[t]{.4\linewidth} |
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| 99 | \includegraphics[width=1\linewidth]{dependence-dev} |
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| 100 | \caption{\label{dependence-dev}Dependence graph at development level} |
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| 101 | \end{minipage}\hfill\begin{minipage}[t]{.4\linewidth} |
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| 102 | \includegraphics[width=1\linewidth]{dependence-test} |
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| 103 | \caption{\label{dependence-test}Dependence graph at validation level} |
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| 104 | \end{minipage} |
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| 105 | \end{figure} |
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