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[12]	1	\begin{figure}\leavevmode\center
	2	\includegraphics[width=.8\linewidth]{architecture-csg}
[21]	3	\caption{\label{archi-csg} software architecture for digital system generation}
[12]	4	%\end{figure}\begin{figure}\leavevmode\center
	5	\mbox{}\vspace*{1ex}\\
[21]	6	\includegraphics[width=1.0\linewidth]{architecture-hls}
	7	\caption{\label{archi-hls} software architecture of hardware accellerator synthesis}
[12]	8	%\end{figure}\begin{figure}\leavevmode\center
	9	\mbox{}\vspace*{1ex}\\
	10	\includegraphics[width=.8\linewidth]{architecture-hpc}
	11	\caption{\label{archi-hpc} software architecture of HPC}
	12	\end{figure}
	13	%
[33]	14	Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc}
	15	summarize the software architecture of the COACH framework we plan to develop.
[12]	16	In figures, the dotted boxes are the softwares or formats that COACH
[21]	17	has to provide.
[12]	18	\vspace*{.75ex}\par
[21]	19	For the system genration presented in figure~\ref{archi-csg}, the conductor
	20	is the tool \verb!CSG! (COACH System Generator). Its inputs are a process
	21	network describing the application to design and the synthesis parameters.
	22	The main parameters are the target hardware architectural template
[12]	23	with its instanciation parameters, the hardware/software mapping of the
[21]	24	tasks, the FPGA device and design constraints.
	25	\verb+CSG+ thus requires an architectural template library, a operating system
	26	library, two system hardware component (CPU, memories, BUS...) libraries
	27	(one for synthesis, one for simulation).
	28	For generating the coprocessor of a task mapped as hardware, \verb+CSG+
	29	controls the HAS tools described below.
	30	From these inputs \verb!CSG! can generate the entire system (both software \&
	31	hardware) either as a SystemC simulator to prototype and explore quickly the
	32	design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
	33	launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the
	34	FPGA device.
[12]	35	\\
[21]	36	%To proove CSG that COACH is open and CSG is really configurable, COACH will
	37	%basically support 3 architecture template (the COACH template based on a
	38	%MIPS processors and a VCI token ring, the Altera template based on the NIOS
	39	%and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus)
	40	%and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced
	41	%by the \mustbecompleted{FIXME:zied} contribution that consists in
	42	%implementing an other hardware target.
	43	%\\
	44	%Finally, it is important to notice that this work is a strong
	45	%enhancement of the SocLib software.
[12]	46	\vspace*{.75ex}\par
[21]	47	The software architecture for HAS is presented in figure~\ref{archi-hls}.
	48	The input is a single task of the process network. The HAS tools do not work
[12]	49	directly on the C++ task description but on an internal format called
[38]	50	\xcoach generated by a plugin into the GNU C compiler (GCC).
	51	This allows on the one hand to insure that all the tools will
[12]	52	accept the same C++ description and on the other hand to make possible
[21]	53	their chaining. The front-end tools read a \xcoach description and generate
	54	a new \xcoach description that exibits more parallelism or implement
	55	specific instructions for ASIP. The back-end tools read a \xcoach
	56	description and generate a \xcoachplus description. This is a \xcoach
	57	description anotated with hardware information (scheduling, binding) required by
	58	the VHDL and systemC drivers.
	59	Furthermore, the back-end tools uses a macro-cell library (functional and memory
	60	unit).
[12]	61	\vspace*{.75ex}\par
[21]	62	In addition to digital system design, HPC requires a supplementary
	63	partitioning step presented in figure~\ref{archi-hpc}. The designer
	64	splits the initial application (tag 1) in two parts: one still on the PC and the
	65	other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data
	66	through communication primitives (tag 2) implemented in a library.
	67	To evaluate if the relevance of the partitioning, the designer can build a
	68	simulator. Once the partitioning is validated, the design of the FPGA part
	69	is done through \verb!CSG! (figure~\ref{archi-csg}).
[12]	70	\vspace*{.75ex}\par
[46]	71	\mustbecompleted{FIXME == MODIFICATION DE LA FIGURE}
[33]	72	The project is split into 8 tasks numbered from 0 to 7.
[12]	73	The first task (task 0) is the project management, the last one (task 7) is
	74	the dissemination the other task are listed below:
	75	\begin{enumerate}
[46]	76	\item\textbf{\Backbone:} This task tackles the fundamental points of the
[21]	77	project such as the defintion of the COACH inputs and outputs,
	78	the internal formats (e.g. \xcoach), the architectural templates and
	79	the design flow.
[46]	80	\item\textbf{System generation:} This task addresses the prototyping and
[21]	81	the generation of digital system. Apart from HAS that belong to the task 3
	82	and 4, its components are those presented figure~\ref{archi-csg}
	83	(e.g. \verb!CSG!, operating systems).
	84	\item\textbf{HAS front-end:} This task mainly focusses on four functionalities:
	85	optimization of the memory usage, parallelism enhancement through loop
	86	transformations, coarse grain parallelization and ASIP generation.
	87	\item\textbf{HAS back-end:} This task groups two functionalities:
	88	High-Level Synthesis of data dominated description and HLS of control
	89	dominated description.
	90	This task contains also the development of a frequency adaptator
	91	that will allow the coprocessors to respect the processor \& the bus
	92	frequency.
	93	\item\textbf{Communication between PC \& FPGA-SoC:}
	94	This task pools the features dedicated to HPC. The main are the
	95	partitioning validation (see figure~\ref{archi-hpc}, the sytem drivers for
	96	both PC and FPGA-SoC sides, the hardware communication components.
[23]	97	\item\textbf{Demonstrators:}
[33]	98	This task groups the demonstrators of the COACH project.
[21]	99	\mustbecompleted{FIXME}
[12]	100	\end{enumerate}
[21]	101	%
[12]	102	\begin{figure}\leavevmode\center
[21]	103	%\includegraphics[width=.4\linewidth]{dependence-task}
	104	\includegraphics[width=0.70\linewidth]{dependence-task-h}
	105	\caption{\label{dependence-task}Task dependencies}
[12]	106	\end{figure}
[21]	107	Figure~\ref{dependence-task} presents the dependencies between the tasks.
	108	"$task-N \longrightarrow task-M$" means that $task-N$ requires $task-M$
	109	to work and be demonstrated. The more bold is the arrow, the more important is
	110	the dependency.
	111	The graph shows:
	112	\begin{itemize}
	113	\item Even that $T3$ and $T4$ functionalities are complementary, their
	114	developments are independent (thanks to \xcoach internal format).
	115	\item $T2$ depends slightly from $T3$ and $T4$. Indeed, $T2$ may works
	116	without $T3$ and $T4$ if we limit to digital systems without hardware
	117	accellerators.
	118	\item $T5$ strongly depends on $T2$ but, $T2$ does not depend at all on
	119	$T5$. So demonstrators ($T6$) of embedded system would not be impacted if
	120	$T5$ would fail.
	121	\item $T1$ drives all the tasks ($T2$, $T3$, $T4$, $T5$) at the heart of
	122	the COACH project.
	123	\item $T7$ and $T0$ respectively depends on and impacts all the other tasks.
	124	\end{itemize}
[33]	125	This organisation offers enough robustness to insure the success of the
	126	project except for the specification task $T1$.
	127
[37]	128	The only critical task in this chart is T1. \label{xcoach-problem}
[33]	129	However, the partners met
	130	10 times (a one day meeting per month) during the last year to prepare the
	131	specification and the project proposal. This gives us a degree of confidence
	132	that T1 will be completed in time.

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