source: anr/section-4.1.tex @ 130

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1\begin{figure}\leavevmode\center
2\includegraphics[width=.8\linewidth]{architecture-csg}
3\caption{\label{archi-csg} Software architecture for digital system generation}
4%\end{figure}\begin{figure}\leavevmode\center
5\mbox{}\vspace*{1ex}\\
6\includegraphics[width=1.0\linewidth]{architecture-hls}
7\caption{\label{archi-hls} Software architecture of hardware accellerator synthesis}
8%\end{figure}\begin{figure}\leavevmode\center
9\mbox{}\vspace*{1ex}\\
10\includegraphics[width=.8\linewidth]{architecture-hpc}
11\caption{\label{archi-hpc} Software architecture of HPC}
12\end{figure}
13%FIXME: la figure ne montre que l'aspect simulation. Intégrer la partie génération (PC API, PCIX, FPGA-IP, bridge vers VCI, SoC API) serait un plus, non ?
14%
15Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc}
16summarize the software architecture of the COACH framework we will develop.
17In figures, the dotted boxes are the softwares or formats that COACH
18has to provide and to support.
19\parlf
20For the system generation presented in figure~\ref{archi-csg}, the conductor
21is the tool \verb!CSG! (COACH System Generator). Its inputs are a process
22network describing the target application and the synthesis parameters.
23The main parameters are the target hardware architectural template
24with its instantiation parameters, the hardware/software mapping of the
25tasks, the FPGA device and design constraints.
26\verb+CSG+ thus requires an architectural template library, an operating system
27library, two system hardware component (CPU, memories, BUS...) libraries
28(one for synthesis, one for simulation).
29For generating the coprocessor of a task mapped as hardware, \verb+CSG+
30controls the HAS tools described below.
31From these inputs \verb!CSG! can generate the entire system (both software \&
32hardware) either as a SystemC simulator to prototype and explore quickly the
33design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
34launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the
35FPGA device\footnote{Additional partial bitstreams are generated in case of
36 dynamic partial reconfiguration}.
37%To proove CSG that COACH is open and CSG is really configurable, COACH will
38%basically support 3 architecture template (the COACH template based on a
39%MIPS processors and a VCI token ring, the Altera template based on the NIOS
40%and AVALON bus, the Xilinx template based on the MICROBLAZE and PLB bus)
41%and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced
42%by the \mustbecompleted{FIXME:zied} contribution that consists in
43%implementing an other hardware target.
44%\\
45%Finally, it is important to notice that this work is a strong
46%enhancement of the SocLib software.
47\parlf
48The software architecture for HAS is presented in figure~\ref{archi-hls}.
49The input is a single task of the process network. The HAS tools do not work
50directly on the C++ task description but on an internal format called
51\xcoach generated by a plugin into the GNU C compiler (GCC).
52This allows on the one hand to insure that all the tools will
53accept the same C++ description and on the other hand to make possible
54their chaining. The front-end tools read a \xcoach description and generate
55a new \xcoach description that exibits more parallelism or implement
56specific instructions for ASIP. The back-end tools read a \xcoach
57description and generate a \xcoachplus description. This is a \xcoach
58description anotated with hardware information (scheduling, binding) required by
59the VHDL and systemC drivers.
60Furthermore, the back-end tools uses a macro-cell library (functional and memory
61unit).
62\parlf
63In addition to digital system design, HPC requires a supplementary
64partitioning step presented in figure~\ref{archi-hpc}. The designer
65splits the initial application (tag 1) in two parts: one still on the PC and the
66other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data
67through communication primitives (tag 2) implemented in a library.
68To evaluate the relevance of the partitioning, the designer can build a
69simulator. Once the partitioning is validated, the design of the FPGA part
70is done through \verb!CSG! (figure~\ref{archi-csg}).
71\parlf
72The project is split into 8 tasks numbered from 1 to 8. There are described
73bellow and detailled in section \ref{task-description}.
74\begin{description}
75\item[Task-1: \textit{Project management}]
76    This task relies to the monitoring of the COACH project.
77\item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the
78        project such as the defintion of the COACH inputs and outputs,
79    the internal formats (e.g. \xcoach), the architectural templates and
80    the design flow.
81\item[task-3: \textit{System generation}] This task addresses the prototyping and
82    the generation of digital system. Apart from HAS that belong to the task 3
83    and 4, its components are those presented figure~\ref{archi-csg}
84    (e.g.  \verb!CSG!, operating systems).
85\item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities:
86    optimization of the memory usage, parallelism enhancement through loop
87    transformations, coarse grain parallelization and ASIP generation.
88\item[Task-5: \textit{HAS back-end}] This task groups two functionalities:
89    High-Level Synthesis of data dominated description and HLS of control
90    dominated description.
91    This task contains also the development of a frequency adaptator
92    that will allow the coprocessors to respect the processor \& the bus
93    frequency.
94\item[Task-6: \textit{PC/FPGA communication middleware}]
95    This task pools the features dedicated to HPC. The main are the
96    partitioning validation (see figure~\ref{archi-hpc}), the sytem drivers for
97    both PC and FPGA-SoC sides, the hardware communication components and
98        support for dynamic partial reconfiguration.
99\item[Task-7: \textit{Industrial demonstrators}]
100    This task groups the demonstrators of the COACH project.
101    Most of them are industrial applications that will be developped with the COACH
102    framework.
103    Others consist in integrating COACH framework as a driver of industrial proprietary
104    design tools.
105\item{Task 8: \textit{Dissemination}}
106    This task relies to the diffusion of the project results.
107    It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!,
108    \verb!T0+24! and \verb!T0+36!)
109    and the publication on a WEB site of a tutorial.
110\end{description}
111%
112\begin{figure}\leavevmode\center
113%\includegraphics[width=.4\linewidth]{dependence-task}
114\includegraphics[width=0.70\linewidth]{dependence-task-h}
115\caption{\label{dependence-task}Task dependencies}
116\end{figure}
117Figure~\ref{dependence-task} presents the tasks dependencies.
118"$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$.
119The more bold is the arrow, the more important is the impact.
120The graph shows:
121\begin{itemize}
122\item Even that $T4$ and $T5$ functionalities are complementary, their
123developments are independent (thanks to \xcoach internal format).
124\item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may works
125without $T4$ and $T5$ if we limit to digital systems without hardware
126accellerators.
127\item $T3$ strongly impacts $T6$ but, $T3$ does not depend at all on
128$T6$. So demonstrators ($T7$) of embedded system would not be impacted if
129$T6$ would fail. 
130\item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) at the heart of
131the COACH project.
132\item The demonstrators developped in $T7$, of course, strongly depends on the achievements
133of the previous tasks ($T2$, $T3$, $T4$, $T5$, $T6$).
134\item $T8$ and $T1$ respectively depends on and impacts all the other tasks.
135\end{itemize}
136This organisation offers enough robustness to insure the success of the
137project except for the specification task $T2$.
138The only critical task in this chart is $T2$. \label{xcoach-problem}
139However, the partners met
14010 times (a one day meeting per month) during the last year to prepare the
141specification and the project proposal. This gives us a degree of confidence
142that $T2$ will be completed in time.
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