source: anr/section-4.4.tex @ 67

Last change on this file since 67 was 56, checked in by coach, 15 years ago

Modifications de TIMA, task-5 et section-3.1 principalement

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1\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90}
2\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99}
3\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7}
4\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7}
5\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4}
6\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24}
7\def\ganttlabelstyle#1{\begin{small}#1\end{small}}
8\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}}
9
10%\begin{figure}\leavevmode\center
11%\hspace*{-.6cm}
12%\input{gantt.tex}
13%\caption{\label{gantt}Gantt diagram of delivrables}
14%\end{figure}
15
16\begin{figure}\leavevmode\center
17\hspace*{-.6cm}\vspace{-1.5cm}
18\input{gantt1.tex}
19\caption{\label{gantt1}Gantt diagram of delivrables (task-1 \& task-8)}
20\end{figure}
21
22\begin{figure}\leavevmode\center
23\hspace*{-.6cm}\vspace{-1.5cm}
24\input{gantt2.tex}
25\caption{\label{gantt2}Gantt diagram of delivrables (task-2 to task-7)}
26\end{figure}
27
28The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project.
29Before the final release (T0+36), there are 4 milestones (red lines on the figures) at
30$T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent
31delivrables.
32\begin{description}
33\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of
34    the demonstatrors as a reference software.
35\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are
36    written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
37    The main restrictions are:
38    1) only the COACH architectural template is supported,
39    2) HAS is not available (but prototyping with virtual coprocessors is available),
40    3) Enhanced communication schemes are not available.
41\item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
42    features are availables.
43    The main restriction is that COACH can not yet generate FPGA-SoC for ALTERA and XILINX
44    architectural templates.
45    The others restriction is that the HAS tools are not yet fully operational.
46\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
47    supported.
48    The main restriction are:
49    1) The HAS tools have not been yet enhanced,
50    2) dynamic partial reconfiguration is not supported,
51    3) \mustbecompleted{FIXME:ALL .....}
52\item[Final Release ($T0+36$)]
53\end{description}
54This organisation allows to advance globally the project step by step mixing development
55and demonstrator delivrables.
56Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
57at the integration phase is significantly reduced.
58\par
59The project has several critical issues:
60\begin{description}
61\item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})]
62    Because all the HAS tools rely on it, it is a
63    crucial task. There are no work-arround but as mentionned in
64    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we have worked on it
65        for a year and are confident.
66\item[\xcoachplus format (\novers{\specXcoachDoc},
67      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
68    Its aim is the generation of the coprocessors (hardware \& prototyping model).
69    By centralizing the coprocessor generation, it guarantees their functioning
70    independently of the used HAS tools.
71        Our experience with UGH and GAUT give us confidence in the succes of this
72        task.
73\item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
74     {\csgXilinxSystemC}]
75     The SocLib component library contains most of the SystemC models used for the
76     prototyping description of the ALTERA and XILINX architectural templates.
77     Nevertheless, at this time we do not know how many are missing and if the existing
78     are really useables.
79     If the work of theses tasks is too important, they will be abandoned.
80     In this case the work-arround to prototype the XILINX and ALTERA architectural
81     templates is to use the COACH one. These architectures being very similar, the
82     simulation results must be proportional. Theses tasks will be changed by measuring
83     the deviance.
84\item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})]
85     If one of these tasks is impossible or too important or leads to inefficiency,
86     it will be abandoned.
87     In this case, the COACH architectural template will not be available for HPC and
88     a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
89     prototyping.
90\end{description}
91
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