source: anr/section-5.tex @ 153

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1\subsection{Dissemination}
2
3The COACH project will bring new scientific results in various fields, such as high level synthesis,
4hardware/software codesign, virtual prototyping, harware oriented compilation techniques,
5automatic parallelisation, etc. These results will be presented in the relevant International
6Conferences, namely DATE, DAC, or ICCAD.
7
8More generally, the COACH infrastructure and the design flow supported by the COACH
9tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
10in various worshops and conferences.
11
12Following the general policy of the SoCLib platform, the COACH project will be an
13open infrastructure, and the COACH tools and libraries will available in the framework
14of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory.
15
16\subsection{Exploitation of results}
17
18The main goal of the COACH project is to help SMEs (Small and Medium Enterprises)
19to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
20Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
21As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus
22on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design)
23tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform :
24
25\begin{itemize}
26\item
27All software tools supporting the COACH design flow will be available as free software.
28All academic partners contributing to the COACH project agreed to distribute the ESL software
29tools under the same GPL license as the SoCLib tools. 
30\item
31The SystemC simulation models for the hardware components
32used by the SoCLib architectural template will be distributed as free software
33under a non-contaminant LGPL license.
34\item
35The synthesizable VHDL models supporting the neutral architectural template
36(corresponding to the SocLib IP cores library), will have two modes of dissemination.
37A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
38also general purpose, reusable components, such as processor cores, memory controllers
39optimised cache controllers, peripheral controllers, or bus controllers.
40For non commercial use (i.e. research or education in an academic context, 
41or feasbility study in an industrial context), the synthesizable VHDL models will be freely available.
42For commercial use, commercial licenses will be negociated between the owners and the customers.
43\item
44The proprietary \altera, \xilinx and \zied IP core libraries are commercial products
45that are not involved by the free software policy, but these libraries will be supported by the
46synthesis tools developped in the COACH project.
47\end{itemize}
48
49This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as
50demonstrated by the "letters of interest" that have been collected during the preparation
51of the project and presented in annexe~\ref{lettre-soutien}.
52
53\subsection{Indusrial Interest in COACH}
54
55\subsubsection*{Partner: \textit{\bull}}
56The team of \bull participating to the COACH project is from the Server Development
57Department who is in charge of developing hardware for open servers (e.g. NovaScale) and
58HPC solutions. The main expectation from COACH is to derive a new component (fine-grain
59FPGA parallelism) to add to existing Bull HPC solutions.
60
61\subsubsection*{Partner: \textit{\xilinx}}
62Computing power potential of our FPGA architectures
63growing very quickly on one side, and complexity of designs implemented
64using our FPGAs dramatically increasing on the other side, it is very
65interesting for us to get high level design methodologies progressing
66quickly and targetting our FPGAs in the most possible efficient way.
67\parlf
68\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
69\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
70future work of our customers.
71
72\subsubsection*{Partner: \textit{\thales}}
73\noindent
74\thales has two main reasons to use the COACH platform:
75\begin{itemize}
76  \item The huge increase of the complexity of the systems in particular by their
77  heterogeneity, raises the issues of design cost and time in the same proportion. The
78  divisions need a design tool which supports the implementation of the applications from
79  algorithm description to the executable code on platforms composed of several general
80  purpose processors and dedicated IPs.
81  \item The applications are more and more complex and adaptable to the environment which
82  leads to a mixture of control aspects and data stream computing aspects. A new approach
83  is necessary to be able to describe this type of application and manage the high level
84  synthesis of system embedding control and data flow aspects.
85\end{itemize}
86\parlf
87TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging
88technologies in its domains of expertise. Specifically in COACH, the studied technology is
89a method and associated tools to make the bridge between application capture at system
90level and the implementation on heterogeneous distributed computing architectures. The
91main stake for Thales behind this is the future design process that will be applied to its
92system teams in the future for the computation-intensive sensor applications. In a context
93of very instable market of tools for parallel programming, it is important to experiment
94and demonstrate the candidate technologies.
95\\
96In its role of internal dissemination, TRT will make the demonstration of the full design
97flow within Thales, and will keep available a platform to later evaluate additional
98applications coming from the Business Units.
99\\
100The COACH platform will be used in the new \thales products in which the algorithms are more
101and more dependent of the environment and have to permanently adapt their behavior in
102varying environments. The target markets are the critical infrastructures security and
103border monitoring.
104
105\subsubsection*{Partner: \textit{\zied}}
106
107\zied is developing a new architecture for embedded system. Our interest in using COACH
108are:
109\begin{itemize}
110  \item firstly, to validate our new architecture by emulating it with COACH.
111  \item Secondly, to use this emulator and the COACH potential to quickly setup
112  demonstrator to our customer.
113\end{itemize}
114
115\subsubsection*{Partner: \textit{\navtel}}
116\navtel has a platform for high performence computation based on ARM processor and FPGAs
117that embedde coprocessors. Currently, the coprocessors are handmade and their designs
118constitute an important part of our product cost. We have try free HLS tools to diminish
119them but the quality of the generated designs was not sufficient to be useable.
120So our interest in COACH is mainly the HLS tools.
121
122\subsubsection*{Industrial supports}
123The following SMEs demonstrate interest to the COACH project (see the "letters of
124interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will
125evaluate it:
126\letterOfInterest{ADACSYS}{lettres/Coach_ADACSYS_lettre_interet},
127\letterOfInterest{MAGILLEM Design Services}{lettres/Coach_lettre_interet_MDS},
128\letterOfInterest{INPIXAL}{lettres/inpixal.jpg}
129
130\letterOfInterestClose
131
132\subsection{Management of Intellectual Property}
133A global consortium agreement will be defined during the first six monts of the project.
134As already stated, the COACH project has been prepared during one year by a monthly meeting
135involving the five academic partners. The general free software policy described in the
136previous section has been agreed by academic partners  and has been
137approved by all industrial participants. This free software policy will
138simplify the definition of the consortium agreement.
139
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