source: anr/section-5.tex @ 67

Last change on this file since 67 was 62, checked in by alain, 15 years ago

Introducing content in sections 5 & 6

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1\subsection{Dissemination}
2
3The Coach project will bring new scientific results in various fields, such as high level synthesis,
4hardware/software codesign, virtual prototyping, harware oriented compilation technics,
5automatic parallelisation, etc. These results will be presented in the relevant International
6Conferences, namely DATE, DAC, or ICCAD.
7
8More generally, the Coach infrastructure and the design flow supported by the Coach
9tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
10in various worshops and conferences.
11
12Following the general policy of the SoCLib platform, the COACH project will be an
13open infrastructure, and the Coach tools and libraries will available in the framework
14of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory.
15
16\subsection{Exploitation of results}
17
18The main goal of the Coach project is to help SMEs (Small and Medium Enterprises)
19to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
20Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
21As the fabrication costs of an ASIC is generally too high for SMEs, the Coach project focus
22on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design)
23tools is an issue, and the Coach project will follow the same general policy as the SoCLib platform :
24
25\begin{itemize}
26\item
27All software tools supporting the Coach design flow will be available as free software.
28All academic partners contributing to the Coach project agreed to distribute the ESL software
29tools under the same GPL license as the SoCLib tools. 
30\item
31The SystemC simulation modelsafor the hardware components
32used by the SoCLib architectural template will be distributed as free software
33under a non-contaminant LGPL license.
34\item
35The synthesizable VHDL models supporting the neutral architectural template
36(corresponding to the SocLib IP cores library), will have two modes of dissemination.
37A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
38also general purpose, reusable components, such as processor cores, memory controllers
39optimised cache controllers, peripheral controllers, or bus controllers.
40For non commercial use (i.e. research or education in an academic context, 
41or feasbility study in an industrial context), the synthesizable VHDL models will be freely available.
42For commercial use, commercial licenses will be negociated between the owners and the customers.
43\item
44The proprietary ALTERA and XILINX IP core libraries are commercial products
45that are not involved by the free software policy, but these libraries will be supported by the
46synthesis tools developped in the Coach project.
47\end{itemize}
48
49This general approach is supported by a large number of SMEs, as demonstrated by the "letters
50of interest" that have been collected during the preparation of the project :
51\begin{itemize}
52\item 
53\item
54\item
55\item
56\item
57\end{itemize}
58
59\subsection{Management of Intellectual Property}
60
61A global consortium agreement will be defined during the first six monts of the project.
62As already stated, the Coach project has been prepared during one tear by a monthly meeting
63involving the five academic partners. The general free software policy described in the
64previous section has been agreed by academic partners  and has been
65approved by all industrial participants. This free software policy will
66simplify the definition of the consortium agreement.
67
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