\subsection{Dissemination}

The Coach project will bring new scientific results in various fields, such as high level synthesis,
hardware/software codesign, virtual prototyping, harware oriented compilation techniques,
automatic parallelisation, etc. These results will be presented in the relevant International
Conferences, namely DATE, DAC, or ICCAD. 

More generally, the Coach infrastructure and the design flow supported by the Coach
tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
in various worshops and conferences.

Following the general policy of the SoCLib platform, the COACH project will be an 
open infrastructure, and the Coach tools and libraries will available in the framework 
of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. 

\subsection{Exploitation of results}

The main goal of the Coach project is to help SMEs (Small and Medium Enterprises) 
to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
As the fabrication costs of an ASIC is generally too high for SMEs, the Coach project focus
on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) 
tools is an issue, and the Coach project will follow the same general policy as the SoCLib platform :

\begin{itemize}
\item
All software tools supporting the Coach design flow will be available as free software.
All academic partners contributing to the Coach project agreed to distribute the ESL software
tools under the same GPL license as the SoCLib tools.  
\item
The SystemC simulation models for the hardware components
used by the SoCLib architectural template will be distributed as free software 
under a non-contaminant LGPL license.
\item
The synthesizable VHDL models supporting the neutral architectural template
(corresponding to the SocLib IP cores library), will have two modes of dissemination.
A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
also general purpose, reusable components, such as processor cores, memory controllers
optimised cache controllers, peripheral controllers, or bus controllers.
For non commercial use (i.e. research or education in an academic context,  
or feasbility study in an industrial context), the synthesizable VHDL models will be freely available.
For commercial use, commercial licenses will be negociated between the owners and the customers.
\item
The proprietary ALTERA, XILINX and FLEXRAS IP core libraries are commercial products
that are not involved by the free software policy, but these libraries will be supported by the 
synthesis tools developped in the Coach project.
\end{itemize}

This general approach is supported by a large number of SMEs, as demonstrated by the "letters
of interest" that have been collected during the preparation of the project :
\begin{itemize}
\item \mustbecompleted{Entreprise 1}
\item \mustbecompleted{Entreprise 2}
\item \mustbecompleted{Entreprise 3}
\item \mustbecompleted{Entreprise 4}
\end{itemize}

\subsection{Management of Intellectual Property}

A global consortium agreement will be defined during the first six monts of the project.
As already stated, the Coach project has been prepared during one year by a monthly meeting 
involving the five academic partners. The general free software policy described in the 
previous section has been agreed by academic partners  and has been
approved by all industrial participants. This free software policy will 
simplify the definition of the consortium agreement.