%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\inria (CAIRN \& COMPSYS teams)}

Inria, the French national institute for research in computer science
and control, operating under the dual authority of the Ministry of
Research and the Ministry of Industry, is dedicated to fundamental and
applied research in information and communication science and
technology (ICST). The Institute also plays a major role in technology
transfer by fostering training through research, diffusion of
scientific and technical information, development, as well as
providing expert advice and participating in international programs.

By playing a leading role in the scientific community in the field and
being in close contact with industry, INRIA is a major participant in
the development of ICST in France. Throughout its eight research
centres in Rocquencourt, Rennes, Sophia Antipolis, Grenoble, Nancy,
Bordeaux, Lille and Saclay, INRIA has a workforce of 3 800, 2 800 of
whom are scientists from INRIA and INRIA's partner organizations such
as CNRS (the French National Center for Scientific Research),
universities and leading engineering schools. They work in 168 joint
research project-teams. Many INRIA researchers are also professors and
approximately 1 000 doctoral students work on theses as part of INRIA
research project-teams.

INRIA develops many partnerships with industry and fosters technology
transfer and company foundation in the field of ICST - some ninety
companies have been founded with the support of INRIA-Transfert, a
subsidiary of INRIA, specialized in guiding, evaluating, qualifying,
and financing innovative high-tech IT start-up companies. INRIA is
involved in standardization committees such as the IETF, ISO and the
W3C of which INRIA was the European host from 1995 to 2002.

INRIA maintains important international relations and exchanges. In
Europe, INRIA is a member of ERCIM which brings together research
institutes from 19 European countries. INRIA is a partner in about 120
FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also
collaborates with numerous scientific and academic institutions abroad
(joint laboratories such as LIAMA, associated research teams, training
and internship programs).\\

Two \inria project-teams participate to this project.
\begin{itemize}
\item CAIRN. The CAIRN group of INRIA Rennes -- Bretagne Atlantique study
reconfigurable system-on-chip, i.e. hardware systems whose
configuration may change before or even during execution. To this end,
CAIRN has 13 permanent researchers and a variable number of PhD students, post-docs and engineers.
CAIRN intends to approach reconfigurable architectures from three
angles: the invention of new reconfigurable platforms, the development
of associated transformation, compilation and synthesis tools, and the
exploration of the interaction between algorithms and architectures.
CAIRN is a joint team with CNRS, INSA of Rennes, University of Rennes 1 and ENS Cachan.

\item COMPSYS. The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team
of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du
Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers
and a variable number of PhD students and post-docs. Its field of
expertise is compilation for embedded system, optimizing compilers
and automatic parallelization. It  has authored or contributed to
several well known libraries for linear programming, polyhedra manipulation
and optimization in general. It has strong industrial cooperations, notably
with ST Microelectronics and Thales.
\end{itemize}


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\tima}
The TIMA laboratory ("Techniques of Informatics and Microelectronics
for integrated systems Architecture") is a public research laboratory
sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
Grenoble Institute of Technology (Grenoble-INP) and Universit� Joseph Fourier
(UJF).
The research topics cover the specification, design, verification, test,
CAD tools and design methods for integrated systems, from analog and
digital components on one end of the spectrum, to multiprocessor
Systems-on-Chip together with their basic operating system on the other end.

Currently, the lab employs 124 persons among which 60 PhD candidates, and runs
32 ongoing French/European funded projects.
Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions
and had 243 PhD thesis defended.

The System Level Synthesis Group (25 people including PhDs) is
involved in several FP6, FP7, CATRENE and ANR projects.
Its field of expertise is in CAD and architecture for Multiprocessor
SoC and Hardware/Software interface.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\ubs}

The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, 
de la Communication, et de la Connaissance), is a French CNRS laboratory 
(UMR 3192) that groups 4 research centers in the west and south 
Brittany: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de 
Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). 
\\
The Lab-STICC is composed of three departments: Microwave and equipments (MOM), 
Digital communications, Architectures and circuits (CACS) and Knowledge, 
information and decision (CID). The Lab-STICC represents a staff of 279 
peoples, including 115 researchers and 113 PhD students. 
The scientific production during the last 4 years represents 20 
books, 200 journal publications, 500 conference publications, 22 
patents, 69 PhDs diploma. 
\par
The UBS/Lab-STICC laboratory is involved in several national research 
projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, 
A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), 
CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE 
...). It is also involved in European Project (e.g. ITEA/SPICES, 
IST/AETHER ...). These projects are conducted through tight cooperation 
with national and international companies and organizations (e.g. France 
Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS, 
BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former 
projects are for example the high-level synthesis tool GAUT, the UHLS 
syntax and semantics-oriented editor, the DSP power estimation tool 
Soft-explorer or the co-design framework Design Trotter.
\\
\par
The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), 
located in Lorient, is involved in COACH. 
The UBS/Lab-STICC is working on the design of complex electronic systems 
and circuits, especially but not exclusively focussing on real-time 
embedded systems, power and energy consumption optimization, high-level 
synthesis and IP design, digital communications, hardware/software 
co-design and ESL methodologies. The application targeted by the 
UBS/Lab-STICC are mainly from telecommunication and multimedia domains 
which enclose signal, image, video, vision, and communication processing.


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\upmc}

University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students). 
The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). 
The \og System on Chip \fg Department of LIP6 consists of  80 people, including 40 PHD students. 
The research focus on CAD tools and methods for VLSI and System on Chip design. 
\parlf
The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. 
The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME, 
OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR. 
\parlf
The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
the SoCLib WEB server.
In the SoCLin platform, the DSX tool is used for design space exploration.
It helps the system designer to describe the coarse grain parallelism of the software application
as a Task and Communication Graph, to configure the hardware architecture, and to map the 
multi-task software application on the multi-processors architecture.
The DSX toll will be extended to support the FPGA target.
Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis
of control-dominated coprocessors.
This tool will be modified to be integrated in the Coach design flow.
\parlf
Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies 
(including \zied) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\xilinx}

\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
\xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex
families) and in the other hand a software solution allowing exploiting the
characteristics of these FPGA.
\parlf
The tools proposed allow the designer to describe his architecture from a modeling
language (VHDL/Verilog) to an optimized architecture implemented to the selected
technology.
The team located at Grenoble is responsible of the logic synthesis tool development (XST)
of the software solution, which aggregates all the steps allowing proceeding from a  HDL
model to a technological netlist:
\begin{itemize}
  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
  \item RTL model optimizations.
  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
  \item Boolean equations generation for random logic.
  \item Logical, mapping and timing optimizations.
\end{itemize}
\parlf
The architectures developed by \xilinx offer a collection of technological primitives
(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
and even configurable processor cores (Pico and MicroBlaze families).
This kind of architecture allows, therefore, the designer to validate different
hardware/software possibilities in a High Level Synthesis (HLS) framework.
\parlf
The classical optimization techniques focus, mainly, on the frequency aspects and on
available resources use.
The optimizations, taking into account the consumption criteria, become critical due to
the fact of the increase of the architecture complexity and due to the use of FPGA
component for low power applications.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\bull}

\bull designs and develops servers and software for an open environment, integrating the
most advanced technologies. It brings to its customers its expertise and know-how to help
them in the transformation of their information systems and to optimize their IT
infrastructure and their applications.
\parlf
\bull is particularly present in the public sector, banking, finance, telecommunication
and industry sectors. Capitalizing on its wide experience, the Group has a thorough
understanding of the business and specific processes of these sectors, thus enabling it to
efficiently advise and to accompany its customers. Its distribution network spreads to
over 100 countries worldwide.
\parlf
The team participating to the COACH project is from the Server Development Department
based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
from architecture specification, ASIC design/verification/prototyping to board design and
include also specific EDA development to complement standard tools.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\thales}

\thales is a world leader for mission critical information systems, with activities in 3
core businesses: aerospace (with all major aircraft manufacturers as customers), defence,
and security (including ground transportation solutions). It employs 68000 people
worldwide, and is present in 50 countries.  \thales develops its strategic capabilities in
component, software and system engineering and architectures through its R \& T organization.
Its six Divisions manage their strategy and technical co-ordination per domain with
hundreds of Units in these Divisions developing their technical activities in close
relationship with their market. In this environment, \thales Research \& Technology
operates at the corporate level as the technical community network architect, in charge of
developing upstream and \thales-wide R \& T activities, with vision and visibility.
In support of \thales applications, TRT's mission is also to anticipate and speed up
technology transfer from research to development in Divisions by developing collaborations
in R\&T.

Thales is international, but Europe-centered. Research \& Development activities are
disseminated, and corporate Research and Technology is concentrated in Centres in France,
the United Kingdom and the Netherlands.
The R\&T in Thales emphasizes more particularly on critical information systems,
processing, control and cognitive systems, and autonomous systems.

A key mission of our R\&T centres is to have a bi-directional transfer, or “impedance
matching” function between the scientific research network and the corresponding
businesses. Benefiting from its presence and visibility on the international scene in
advanced sciences, technology and software, \thales Research \& Technology is perceived as
a valuable partner of the best research centres (academic or industrial) through
recognized scientists and research engineer participation in collaborative projects.
The TRT’s Information Science and Technology Group is able to develop innovative solutions
along the information chain exploiting sensors data, through expertise in: computational
architectures in embedded systems, typically suitable for autonomous system environments,
mathematics and technologies for decision involving information fusion and cognitive
processing, and cooperative technologies including man system interaction.
The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the
Information Science and Technology Group.

Like other labs of TRT, ESL is in charge of making the link between the needs from Thales
business units and the emerging technologies, in particular through assessment and
de-risking studies.
It has a long experience on parallel architectures design, in particular on SIMD
architectures used for image processing and signal processing applications and on
reconfigurable architectures.
ESL is also strongly involved in studies on programming tools for these types of
architectures and has developed the SpearDE tool used in this project.
The laboratory had coordinated the FP6 IST MORPHEUS project on reconfigurable technology,
being highly involved in the associated programming toolset.

The team is also involved in
the FP6 IST FET AETHER project on self-adaptability technologies and coordinates national
projects on MPSoC architecture and tools like the \verb+Ter@ops+ project (P\^{o}le de
Comp\'{e}titivit\'{e} \verb+System@tic+) dedicated to the design of a MPSoC for intensive
computing embedded systems.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\zied}

\zied is an innovative start-up specialized in the conception of configurable circuits
and the development of CAD tools. \zied provides a complete front-to-back-end generator
of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs.
\zied solution is based on a patented FPGA architecture delivering an unprecedented
level of logic density. This high capacity is accessible using a traditional RTL flow from
Verilog/VHDL synthesis all the way to bitstream generation.

\zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the
French National Competition for Business Startup and Innovative Technology in 2007 and
2009 in “emergence” and “creation” categories respectively.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\navtel}

\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
focuses on intelligent signal mining for knowlege based signal processing systems. 
The company main activity covers the following domains: satellite communication,
aeronautics, imaging and security.
\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
and imaging systems and 30\% to its own research programmes in collaboration with French
and international partners.
\parlf
The multi disciplinary technical team comprises 6 engineers for signal processing and
hardware development and one technician.
\parlf
\navtel has its own Ph.D program which includes in the past (classification technology
and MIMO for FPGA implementation) and currently the preparation of a project for remote
sensing with signal intelligence for satellite application. The company participates in
national and European level projects contributing to a strategic alliance between academic
and  industrial partners.\\
The current research covers particle filter applications for communication and RADAR,
Cognitive Radio, Satellite communication, embedded super computing and focuses on low
power algorithms for implementation in FPGA and  soft computing.
\parlf
For manufacturing and industrialization, \navtel works with ISO certified partners.
The company clients include the CNES, Thalès Alenia Space, Thalès Communication, EADS,
Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the
system delivery.

\begin{description}
\item[Recognitions:]\mbox{}
\begin{itemize}
  \item EC Challenge+  programme for innovative projects (promotion 9)
  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
  \item Recognition by the French Senate for company creation  during the
        \og Semaine de l'entrepreneur \fg 2005.
\end{itemize}
\end{description}