source: anr/section-consortium-desc.tex @ 356

\anrdoc{(maximum 0,5 page par partenaire) Decrire brievement chaque
partenaire et fournir ici les elements permettant d'apprecier la
qualification des partenaires dans le projet (le \og pourquoi qui fait quoi
\fg). Il peut s'agir de realisations passees, d'indicateurs (publications,
brevets), de l'interet du partenaire pour le projet.\\
Montrer la complementarite et la valeur ajoutee des cooperations entre les
differents partenaires. L'interdisciplinarite et l'ouverture à diverses
collaborations seront à justifier en accord avec les orientations du
projet. (1 page maximum)}

The consortium is made of 8 partners: 5 academic and 3 industrial, which is well balanced 
for reaching the objectives (technical innovation and industrial evaluation for further exploitation).
Each academic partner is expert in a few area and each industrial brings a
different approach to the use of the tools.
\parlf
The expertise domains of academic partners are
MPSoC design \& virtual prototyping (\upmc, \tima),
micro-architecture design (\upmc, \tima, \ubs), 
HLS (\upmc, \tima, \ubs),
embedded OS (\tima), 
compilation (\ubs, \lip),
polyhedral model (\lip),
HPC (\lip, \upmc) and
ASIP design (\inria).
These domains cover all the COACH aspects.
\parlf
The approach to the use of the tools of industrials are: 
IP-XACT and industrial flow integration (\mds),
HPC (\bull) and
\mustbecompleted{XXX "par MAGILEM ou TRT"} (\thales).
\thales will represent the FPGA users, \bull the HPC users, and \mds the SoC integrators.

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\subsubsection{\mdslong}

Magillem Design Services has been established by a team of seasoned engineers and a 
group of business angels in the fall of 2006. The company has inherited Magillem, a 
robust and innovative technology worth 120 man years. The Magillem environment is 
dedicated to the design, verification and flow management of complex HW/SW based on IP-XACT. 
In the service area, we audit the existing industrial flows and propose a work plan to 
adapt them to IP-XACT, we validate and verify the full compatibility of tools interfaces
into a flow testbench, we test the IP deliverables against a benchmark for compliance 
using our IP-XACT packager, and check IP integration properties onto a test system.
Magillem's tools are used in the most advanced production flows of integrated circuit 
manufacturers (ST, NXP, TI, Qualcomm, etc.) and are linked with the research work of 
the best laboratories of the domain (LIP6, TIMA, Fhg, OFFIS, etc.). Our participation 
to leading European collaborative projects (e.g. IST COMPLEX, SPRINT, ICODES, etc.) 
allow us to maintain a high level of innovation around our core technology: SoC design
methodologies at ESL, design and verification in AMS domain, HW/SW co-design, safety
and security of systems.
Beyond this core technology domain, Magillem has evolved with the tool suite called
Revenge, answering to wider assembly issues for large heterogeneous systems.

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\subsubsection{\upmc}

University Pierre et Marie Curie (UPMC) is the largest university in France (7400
employees, 38000 students).
The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of
UPMC, hosting more than 400 researchers, under the umbrella of the CNRS (Centre National
de la Recherche Scientifique).
The \og System on Chip \fg Department of LIP6 consists of 40 permanent
researchers and 40 PHD students.
The research focuses on CAD tools and methods for VLSI and System on Chip design. 
\parlf
The SoC department has been involved in several projects: IDPS, EVEREST,
OMI-HIC/MACRAME/\-ARCHES, EUROPRO, COSY, Medea SMT/MESA/+, BDREAMS, SoCLib, TSAR.
It developed and maintains the public domain VLSI CAD system ALLIANCE that is installed in more than
200 universities worldwide. It is also in charge of the SoCLib technical
coordination and WEB server.
\parlf
Even if the preferred dissemination policy for the COACH design flow will be the free
software policy, the SoC department is ready to support start-ups :
Six startup companies have been created by former
researchers from  the SoC department of LIP6 between 1997 and 2002.
%The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. 
%The SoCLib DSX component was designed and developped in our laboratory.
%It allows design space exploration and will the base of the $CSG$ COACH tools.
%Moreover, the LIP6 developed during the last 10 years the UGH tool for high level
%synthesis of control-dominated coprocessors.
%This tool will be modified to be integrated in the COACH design flow.

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\subsubsection{\ubs}

The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, 
de la Communication, et de la Connaissance), is a French CNRS laboratory 
(UMR 3192) that groups 4 research centers in the west and south 
Brittany.
%: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de 
%Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). 
%The Lab-STICC is composed of three departments: Microwave and equipments (MOM), 
%Digital communications, Architectures and circuits (CACS) and Knowledge, 
%information and decision (CID).
It represents a staff of 279 peoples, including 115 researchers and 113 PhD
students.
The scientific production during the last 4 years represents 20 
books, 200 journal publications, 500 conference publications, 22 
patents and 69 PHDs diploma. 
\parlf
%The UBS/Lab-STICC laboratory is involved in several national research 
%projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, 
%A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), 
%CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE 
%...). It is also involved in European Project (e.g. ITEA/SPICES, 
%IST/AETHER ...).
The UBS/Lab-STICC laboratory is involved in several projects (SystemC'Mantic,
EPICURE, MILPAT, ALIPTA, A3S, MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE,
ICTER, COSIP,  PALMYRE, ITEA/SPICES, IST/AETHER.
%These projects are conducted through tight cooperation 
%with national and international companies and organizations (e.g. France 
%Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS, 
%BarCo, STMicroelectronics, Alcatel-Lucent ...).
%Results of those or former 
%projects are for example the high-level synthesis tool GAUT, the UHLS 
%syntax and semantics-oriented editor, the DSP power estimation tool 
%Soft-explorer or the co-design framework Design Trotter.
\parlf
The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), 
located in Lorient, is involved in COACH. 
The UBS/Lab-STICC is working on the design of complex electronic systems 
and circuits, especially but not exclusively focussing on real-time 
embedded systems, power and energy consumption optimization, high-level 
synthesis and IP design, digital communications, hardware/software 
co-design and ESL methodologies. The application targeted by the 
UBS/Lab-STICC are mainly from telecommunication and multimedia domains 
which enclose signal, image, video, vision, and communication processing.

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\subsubsection{\liplong}
The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team
of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du
Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers
and a variable number of PhD students and post-docs. Its field of
expertise is compilation for embedded system, optimizing compilers
and automatic parallelization. Its members were among the initiators
of the polyhedral model for automatic parallelization and program
optimization generally. It  has authored or contributed to
several well known libraries for linear programming, polyhedra manipulation
and optimization in general. It has strong industrial cooperations, notably
with ST Microelectronics and \thales.

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\subsubsection{\tima}
The TIMA laboratory ("Techniques of Informatics and Microelectronics
for integrated systems Architecture") is a public research laboratory
sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
Grenoble Institute of Technology (Grenoble-INP) and Universit\'{e} Joseph Fourier
(UJF).
The research topics cover the specification, design, verification, test,
CAD tools and design methods for integrated systems, from analog and
digital components on one end of the spectrum, to multiprocessor
Systems-on-Chip together with their basic operating system on the other end.
\parlf
Currently, the lab employs 124 persons among which 60 PhD candidates, and runs
32 ongoing French/European funded projects.
Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions
and had 243 PhD thesis defended.
\parlf
The System Level Synthesis Group (25 people including PhDs) is
involved in several FP6, FP7, CATRENE and ANR projects.
Its field of expertise is in CAD and architecture for Multiprocessor
SoC and Hardware/Software interface.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\inria}

INRIA, the French national institute for research in computer science
and control, operating under the dual authority of the Ministry of
Research and the Ministry of Industry, is dedicated to fundamental and
applied research in information and communication science and
technology (ICST).
It has workforce of 3800 persons that work in 168 joint research project-teams.
\parlf
The Institute plays a major role in technology
transfer by fostering training through research, diffusion of
scientific and technical information, development, as well as
providing expert advice and participating in international programs.
Being in close contact with industry, INRIA is a major participant in
the development of ICST in France.
\parlf
The CAIRN group of INRIA Rennes -- Bretagne Atlantique study reconfigurable
system-on-chip, i.e. hardware systems whose configuration may change before or even during
execution.
To this end, CAIRN has 13 permanent researchers and a variable number of PhD
students, post-docs and engineers.
CAIRN intends to approach reconfigurable architectures from three
angles: the invention of new reconfigurable platforms, the development
of associated transformation, compilation and synthesis tools, and the
exploration of the interaction between algorithms and architectures.
CAIRN is a joint team with CNRS, University of Rennes 1 and ENS Cachan.
%By playing a leading role in the scientific community in the field and
%Throughout its eight research centres in Rocquencourt, Rennes, Sophia Antipolis,
%Grenoble, Nancy, Bordeaux, Lille and Saclay, INRIA has a workforce of 3800, 2800
%of whom are scientists from INRIA and INRIA's partner organizations such as CNRS
%(the French National Center for Scientific Research), universities and leading
%engineering schools.
%They work in 168 joint research project-teams.
%Many INRIA researchers are also professors and approximately 1 000 doctoral
%students work on theses as part of INRIA research project-teams.
%\parlf
%INRIA develops many partnerships with industry and fosters technology
%transfer and company foundation in the field of ICST - some ninety
%companies have been founded with the support of INRIA-Transfert, a
%subsidiary of INRIA, specialized in guiding, evaluating, qualifying,
%and financing innovative high-tech IT start-up companies. INRIA is
%involved in standardization committees such as the IETF, ISO and the
%W3C of which INRIA was the European host from 1995 to 2002.
%\parlf
%INRIA maintains important international relations and exchanges. In
%Europe, INRIA is a member of ERCIM which brings together research
%institutes from 19 European countries. INRIA is a partner in about 120
%FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also
%collaborates with numerous scientific and academic institutions abroad
%(joint laboratories such as LIAMA, associated research teams, training
%and internship programs).

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\bull}

\bull designs and develops servers and software for an open environment, integrating the
most advanced technologies. It brings to its customers its expertise and know-how to help
them in the transformation of their information systems and to optimize their IT
infrastructure and their applications.
\parlf
\bull is particularly present in the public sector, banking, finance, telecommunication
and industry sectors. Capitalizing on its wide experience, the Group has a thorough
understanding of the business and specific processes of these sectors, thus enabling it to
efficiently advise and to accompany its customers. Its distribution network spreads to
over 100 countries worldwide.
\parlf
The team participating to the COACH project is from the Server Development Department
based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
from architecture specification, ASIC design/verification/prototyping to board design and
include also specific EDA development to complement standard tools.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{\thales}

\thales is a world leader for mission critical information systems, with activities in 3
core businesses (aerospace, defence, security).
It employs 68000 people worldwide, and is present in 50 countries.
TRT (\thales Research \& Technology) operates at the corporate level as the technical
community network architect, in charge of developing upstream and \thales-wide
R\&T activities, with vision and visibility.
In support of \thales applications, TRT's mission is also to anticipate and
speed up technology transfer from research to development in Divisions by
developing collaborations in R\&T.
%\thales is international, but Europe-centered.
%Research \& Development activities are disseminated, and corporate Research and
%Technology is concentrated in Centres in France, the United Kingdom and the
%Netherlands.
%A key mission of our R\&T centres is to have a bi-directional transfer, or
%"impedance matching" function between the scientific research network and the
%corresponding businesses.
%The TRT's Information Science and Technology Group is able to develop innovative
%solutions along the information chain exploiting sensors data, through expertise
%in: computational architectures in embedded systems, typically suitable for
%autonomous system environments, mathematics and technologies for decision
%involving information fusion and cognitive processing, and cooperative
%technologies including man system interaction.
The Embedded System Laboratory (ESL) involved in the COACH project is part of
TRT, it is based in Centres (France).
\parlf
Like other labs of TRT, ESL is in charge of making the link between the needs
from \thales business units and the emerging technologies, in particular through
assessment and de-risking studies.
It has a long experience on parallel architectures design, in particular on SIMD architectures used for
image processing and signal processing applications and on reconfigurable architectures.
ESL is also strongly involved in studies on programming tools for these types of
architectures and has developed the SpearDE tool used in this project.
\parlf
The laboratory has coordinated the FP6 IST MORPHEUS project on reconfigurable
technology.% being highly involved in the associated programming toolset.
The team has also been involved in the FP6 IST FET AETHER project on
self-adaptability technologies and coordinated national projects on MPSoC
architecture and tools like the Ter\verb+@+ops project (P\^{o}le de
Comp\'{e}titivit\'{e} System\verb+@+tic).  %dedicated to the design of a MPSoC for intensive computing embedded systems.
%
%\thales is a world leader for mission critical information systems, with activities in 3
%core businesses: aerospace (with all major aircraft manufacturers as customers), defence,
%and security (including ground transportation solutions). It employs 68000 people
%worldwide, and is present in 50 countries. \thales Research \& Technology operates at the
%corporate level as the technical community network architect, in charge of developing
%upstream and \thales-wide R \& T activities, with vision and visibility. In support of
%\thales applications, TRT's mission is also to anticipate and speed up technology transfer
%from research to development in Divisions by developing collaborations in R\&T. \thales is
%international, but Europe-centered. Research \& Development activities are disseminated,
%and corporate Research and Technology is concentrated in Centres in France, the United
%Kingdom and the Netherlands. A key mission of our R\&T centres is to have a bi-directional
%transfer, or "impedance matching" function between the scientific research network and the
%corresponding businesses. The TRT's Information Science and Technology Group is able to
%develop innovative solutions along the information chain exploiting sensors data, through
%expertise in: computational architectures in embedded systems, typically suitable for
%autonomous system environments, mathematics and technologies for decision involving
%information fusion and cognitive processing, and cooperative technologies including man
%system interaction.
%\parlf
%The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the
%Information Science and Technology Group. Like other labs of TRT, ESL is in charge of
%making the link between the needs from \thales business units and the emerging
%technologies, in particular through assessment and de-risking studies. It has a long
%experience on parallel architectures design, in particular on SIMD architectures used for
%image processing and signal processing applications and on reconfigurable architectures.
%ESL is also strongly involved in studies on programming tools for these types of
%architectures and has developed the SpearDE tool used in this project. The laboratory had
%coordinated the FP6 IST MORPHEUS project on reconfigurable technology, being highly
%involved in the associated programming toolset. The team has also been involved in the FP6 IST
%FET AETHER project on self-adaptability technologies and coordinated national projects on
%MPSoC architecture and tools like the Ter\verb+@+ops project (P\^{o}le de
%Comp\'{e}titivit\'{e} System\verb+@+tic) dedicated to the design of a MPSoC for intensive
%computing embedded systems.