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1\anrdoc{A titre indicatif: 2 pages pour ce chapitre.\\
2Presenter les strategies de valorisation des resultats:
3\begin{itemize}
4\item la communication scientifique;
5\item la communication aupres du grand public (un budget specifique peut être prevu),
6\item la valorisation des resultats attendus,
7\item les retombees scientifiques, techniques, industrielles, economiques, ...
8\item la place du projet dans la strategie industrielle des entreprises partenaires du projet
9\item autres retombees (normalisation, information des pouvoirs publics, ...)
10\item les echeances et la nature des retombees technico- economiques attendues
11\item l'incidence eventuelle sur l'emploi, la creation d'activites nouvelles.
12\end{itemize}
13Presenter les grandes lignes des modes de protection et d'exploitation des resultats\\
14Pour les projets partenariaux organismes de recherche/entreprises, les
15partenaires devront conclure, sous l'egide du coordinateur du projet, un
16accord de consortium dans un delai de un an si le projet est retenu pour
17financement.\\
18Pour les projets academiques, l'accord de consortium n'est pas obligatoire
19mais fortement conseille.}
20
21\subsection{Dissemination}
22
23The COACH project will bring new scientific results in various fields, such as high level synthesis,
24hardware/software codesign, virtual prototyping, hardware oriented compilation techniques,
25automatic parallelization, etc. These results will be published in relevant International
26Conferences, namely DATE, DAC, or ICCAD.
27\\
28More generally, the COACH infrastructure and the design flow supported by the COACH
29tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
30in various workshops and conferences (DATE, DAC, CODES+ISSS...).
31\parlf
32Several COACH partners being members of the HiPEAC European Network of Excellence
33(High Performance and Embedded Architecture and Compilation), courses will be proposed for the
34HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems.
35\parlf
36The COACH project will be an open infrastructure, and the COACH tools and libraries will be available via
37a WEB server. This server will be maintained by the UPMC/LIP6 laboratory.
38\\
39On the standardization side, some effort will be made for analysing how the work around IP-XACT
40could be donated for the evolution of the IEEE 1685 standard. \mds is board member of
41Accellera, TRT, TIMA and LIP6 are members, so we'll try to have some influence and at least
42communicate on the fact that our solutions will be compatible with the standard.
43
44\subsection{Industrial exploitation of results}
45
46The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) and even small design team in bigger entities
47to enter the world of MPSoC technologies. For small companies or design services, the cost is a primary concern.
48Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
49As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus
50on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design)
51tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform :
52
53\begin{itemize}
54\item
55All software tools supporting the COACH design flow will be available as free software.
56All academic partners contributing to the COACH project agreed to distribute the ESL software
57tools under the same GPL license.
58\item
59The SystemC simulation models for the hardware components
60used by the SoCLib architectural template will be distributed as free software
61under a non-contaminant LGPL license.
62\item
63The synthesizable VHDL models supporting the neutral architectural template
64(corresponding to the SocLib IP cores library), will have two modes of dissemination.
65A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
66also general purpose, reusable components, such as processor cores, memory controllers
67optimised cache controllers, peripheral controllers, or bus controllers.
68For non commercial use (i.e. research or education in an academic context, 
69or feasibility study in an industrial context), the synthesizable VHDL models will be freely available.
70For commercial use, commercial licenses will be negotiated between the owners and the customers.
71\item
72The proprietary \altera and \xilinx IP core libraries are commercial products
73that are not involved by the free software policy, but these libraries will be supported by the
74synthesis tools developed in the COACH project.
75\item
76\mds will propose a commercial version of COACH, integrated into \mds tool suite and compatible with a standard IP-XACT flow.
77This version will integrate some generic features, already available for
78production (some of them from standard \mds pack, some other developed in
79COACH). Other COACH features will have to be tailored for the specifics of the
80customer framework and will generate service business.
81\end{itemize}
82
83This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as
84demonstrated by the "letters of interest" that have been collected during the preparation
85of the project and presented in annexe~\ref{lettre-soutien}.
86
87\subsection{Industrial Interest in COACH}
88
89\subsubsection*{Partner: \textit{\mds}}
90The interest for \mds in this project is multiple.
91\begin{itemize}
92\item
93We will collaborate in experiments for the integration of High Level Synthesis
94engines into IP-XACT based flow.  This point will be very valuable because more
95and more system integrators are using or considering to use HLS in their flow
96(e.g. Astrium, Airbus, etc.).
97\item
98\mds has already a leading position in the usage of IP-XACT standard for
99managing innovative SoC design methodologies. This project will allow to keep
100the advance in regards with competition by anticipating the next generation
101platforms hosting multi-cores and programmable logic for coprocessors.
102\item
103HPC is a topic that was not covered yet by \mds with its customers. Thanks to
104this project, \mds will collaborate with BULL on this point and this will open
105us doors for new customers market.
106\item
107This project has been set up for maximizing the industrial exploitation of results.
108The role of \mds will be to ensure this objective and after the project, we
109expect a growing contribution for rising the turnover
110(2015: 2 new customers = 100 k\euro,
111 2016: 4 new customers = 250 k\euro,
112 2017: 5 new customers = 400 k\euro).
113These numbers are not high but we tried to keep them realistic.
114The return on investment is nevertheless important and we can also expect side
115effects of this project on sales with existing customers and prospects
116interested in the global \mds solution.
117\end{itemize}
118
119\subsubsection*{Partner: \textit{\bull}}
120\noindent
121The Bull team participating to COACH is from the Server Design and Development Division,
122who is in charge of developing hardware for open servers (e.g.: NovaSacle, Bullion) and
123HPC solutions. With this participation, Bull demonstrates its high interest in the outcome of
124COACH. Effectively, it is now commonly recognized that the future of HPC will be based
125on hybrid architectures in which FPGA will play a major role in the development of configurable
126hardware accelerators by providing the best fine grain parallelism.
127
128\subsubsection*{Partner: \textit{\thales}}
129\noindent
130\thales has two main reasons to use the COACH platform:
131\begin{itemize}
132  \item The huge increase of the complexity of the systems in particular by their
133  heterogeneity, raises the issues of design cost and time in the same proportion. The
134  divisions need a design tool which supports the implementation of the applications from
135  algorithm description to the executable code on platforms composed of several general
136  purpose processors and dedicated IPs.
137  \item The applications are more and more complex and adaptable to the environment which
138  leads to a mixture of control aspects and data stream computing aspects. A new approach
139  is necessary to be able to describe this type of application and manage the high level
140  synthesis of system embedding control and data flow aspects.
141\end{itemize}
142%
143TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging
144technologies in its domains of expertise. Specifically in COACH, the studied technology is
145a method and associated tools to make the bridge between application capture at system
146level and the implementation on heterogeneous distributed computing architectures. The
147main stake for Thales behind this is the future design process that will be applied to its
148system teams in the future for the computation-intensive sensor applications. In a context
149of very instable market of tools for parallel programming, it is important to experiment
150and demonstrate the candidate technologies.
151\\
152In its role of internal dissemination, TRT will make the demonstration of the full design
153flow within Thales, and will keep available a platform to later evaluate additional
154applications coming from the Business Units.
155\\
156The COACH platform will be used in the new \thales products in which the algorithms are more
157and more dependent of the environment and have to permanently adapt their behavior in
158varying environments. The target markets are the critical infrastructures security and
159border monitoring.
160
161\subsubsection*{Industrial supports}
162
163The following SMEs demonstrate interest to the COACH project (see the "letters of
164interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will
165evaluate it:
166\letterOfInterest{ALTERA Corporation}{lettres-2011/Altera1.pdf},
167\letterOfInterestPlus{lettres-2011/Altera2.pdf}
168\letterOfInterest{FlexRAS Technologies}{lettres-2011/Flexras.pdf},
169\letterOfInterest{INPIXAL}{lettres-2011/Inpixal.jpg},
170\letterOfInterest{CAMKA System}{lettres-2011/Camka.pdf},
171\letterOfInterest{RENESAS Design}{lettres-2011/Renesas-dossier.jpg},
172\letterOfInterest{EADS-ASTRIUM}{lettres-2011/Astrium.pdf}.
173%\letterOfInterest{ADACSYS}{lettres-2011/Coach_ADACSYS_lettre_interet},
174%\letterOfInterest{ATEME}{lettres-2011/ATEME.pdf},
175%\letterOfInterest{ALSIM Simulateur}{lettres-2011/Alsim.pdf},
176%\letterOfInterest{SILICOMP-AQL}{lettres-2011/itlabs.pdf},
177%\letterOfInterest{ABOUND Logic}{lettres-2011/abound.pdf},
178\letterOfInterestClose
179
180\subsection{Management of Intellectual Property}
181A global consortium agreement will be defined during the first six monts of the project.
182As already stated, the COACH project has been prepared during one year by a monthly meeting
183involving the five academic partners. The general free software policy described in the
184previous section has been agreed by academic partners  and has been
185approved by all industrial participants. This free software policy will
186simplify the definition of the consortium agreement.
187
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