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1\anrdoc{A titre indicatif: 2 pages pour ce chapitre.\\
2Presenter les strategies de valorisation des resultats:
3\begin{itemize}
4\item la communication scientifique;
5\item la communication aupres du grand public (un budget specifique peut être prevu),
6\item la valorisation des resultats attendus,
7\item les retombees scientifiques, techniques, industrielles, economiques, ...
8\item la place du projet dans la strategie industrielle des entreprises partenaires du projet
9\item autres retombees (normalisation, information des pouvoirs publics, ...)
10\item les echeances et la nature des retombees technico- economiques attendues
11\item l'incidence eventuelle sur l'emploi, la creation d'activites nouvelles.
12\end{itemize}
13Presenter les grandes lignes des modes de protection et d'exploitation des resultats\\
14Pour les projets partenariaux organismes de recherche/entreprises, les
15partenaires devront conclure, sous l'egide du coordinateur du projet, un
16accord de consortium dans un delai de un an si le projet est retenu pour
17financement.\\
18Pour les projets academiques, l'accord de consortium n'est pas obligatoire
19mais fortement conseille.}
20
21\subsection{Dissemination}
22
23The COACH project will bring new scientific results in various fields, such as high level synthesis,
24hardware/software codesign, virtual prototyping, hardware oriented compilation techniques,
25automatic parallelisation, etc. These results will be published in relevant International
26Conferences, namely DATE, DAC, or ICCAD.
27
28More generally, the COACH infrastructure and the design flow supported by the COACH
29tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
30in various worshops and conferences (DATE, DAC, CODES+ISSS...).
31
32Several COACH partners being members of the HiPEAC European Network of Excellence
33(High Performance and Embedded Architecture and Compilation), courses will be proposed for the
34HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems.
35
36Following the general policy of the SoCLib platform, the COACH project will be an
37open infrastructure, and the COACH tools and libraries will be available in the framework
38of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory.
39
40\subsection{Exploitation of results}
41
42The main goal of the COACH project is to help SMEs (Small and Medium Enterprises)
43to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
44Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
45As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus
46on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design)
47tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform :
48
49\begin{itemize}
50\item
51All software tools supporting the COACH design flow will be available as free software.
52All academic partners contributing to the COACH project agreed to distribute the ESL software
53tools under the same GPL license as the SoCLib tools. 
54\item
55The SystemC simulation models for the hardware components
56used by the SoCLib architectural template will be distributed as free software
57under a non-contaminant LGPL license.
58\item
59The synthesizable VHDL models supporting the neutral architectural template
60(corresponding to the SocLib IP cores library), will have two modes of dissemination.
61A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
62also general purpose, reusable components, such as processor cores, memory controllers
63optimised cache controllers, peripheral controllers, or bus controllers.
64For non commercial use (i.e. research or education in an academic context, 
65or feasibility study in an industrial context), the synthesizable VHDL models will be freely available.
66For commercial use, commercial licenses will be negotiated between the owners and the customers.
67\item
68The proprietary \altera and \xilinx IP core libraries are commercial products
69that are not involved by the free software policy, but these libraries will be supported by the
70synthesis tools developed in the COACH project.
71\end{itemize}
72
73This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as
74demonstrated by the "letters of interest" that have been collected during the preparation
75of the project and presented in annexe~\ref{lettre-soutien}.
76
77\subsection{Indusrial Interest in COACH}
78
79\subsubsection*{Partner: \textit{\mds}}
80
81\mustbecompleted{A COMPLETER: Emmanuel ....}
82
83\subsubsection*{Partner: \textit{\bull}}
84The team of \bull participating to the COACH project is from the Server Development
85Department who is in charge of developing hardware for open servers (e.g. NovaScale) and
86HPC solutions. The main expectation from COACH is to derive a new component (fine-grain
87FPGA parallelism) to add to existing Bull HPC solutions.
88
89%\subsubsection*{Partner: \textit{\xilinx}}
90%Computing power potential of our FPGA architectures
91%growing very quickly on one side, and complexity of designs implemented
92%using our FPGAs dramatically increasing on the other side, it is very
93%interesting for us to get high level design methodologies progressing
94%quickly and targetting our FPGAs in the most possible efficient way.
95%\parlf
96%\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
97%\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
98%future work of our customers.
99
100\subsubsection*{Partner: \textit{\thales}}
101\noindent
102\thales has two main reasons to use the COACH platform:
103\begin{itemize}
104  \item The huge increase of the complexity of the systems in particular by their
105  heterogeneity, raises the issues of design cost and time in the same proportion. The
106  divisions need a design tool which supports the implementation of the applications from
107  algorithm description to the executable code on platforms composed of several general
108  purpose processors and dedicated IPs.
109  \item The applications are more and more complex and adaptable to the environment which
110  leads to a mixture of control aspects and data stream computing aspects. A new approach
111  is necessary to be able to describe this type of application and manage the high level
112  synthesis of system embedding control and data flow aspects.
113\end{itemize}
114\parlf
115TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging
116technologies in its domains of expertise. Specifically in COACH, the studied technology is
117a method and associated tools to make the bridge between application capture at system
118level and the implementation on heterogeneous distributed computing architectures. The
119main stake for Thales behind this is the future design process that will be applied to its
120system teams in the future for the computation-intensive sensor applications. In a context
121of very instable market of tools for parallel programming, it is important to experiment
122and demonstrate the candidate technologies.
123\\
124In its role of internal dissemination, TRT will make the demonstration of the full design
125flow within Thales, and will keep available a platform to later evaluate additional
126applications coming from the Business Units.
127\\
128The COACH platform will be used in the new \thales products in which the algorithms are more
129and more dependent of the environment and have to permanently adapt their behavior in
130varying environments. The target markets are the critical infrastructures security and
131border monitoring.
132
133\subsubsection*{Industrial supports}
134
135\mustbecompleted{NON A JOUR}
136The following SMEs demonstrate interest to the COACH project (see the "letters of
137interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will
138evaluate it:
139\letterOfInterest{ALTERA Corporation}{lettres/Altera1.pdf},
140\letterOfInterestPlus{lettres/Altera2.pdf}
141\letterOfInterest{ADACSYS}{lettres/Coach_ADACSYS_lettre_interet},
142\letterOfInterest{MAGILLEM Design Services}{lettres/Coach_lettre_interet_MDS},
143\letterOfInterest{INPIXAL}{lettres/inpixal.jpg},
144\letterOfInterest{CAMKA System}{lettres/CAMKA-System.pdf},
145\letterOfInterest{ATEME}{lettres/ATEME.pdf},
146\letterOfInterest{ALSIM Simulateur}{lettres/Alsim.pdf},
147\letterOfInterest{SILICOMP-AQL}{lettres/itlabs.pdf},
148\letterOfInterest{ABOUND Logic}{lettres/abound.pdf},
149\letterOfInterest{EADS-ASTRIUM}{lettres/Astrium1.pdf}.
150\letterOfInterestPlus{lettres/Astrium2.pdf}
151
152\letterOfInterestClose
153
154\subsection{Management of Intellectual Property}
155A global consortium agreement will be defined during the first six monts of the project.
156As already stated, the COACH project has been prepared during one year by a monthly meeting
157involving the five academic partners. The general free software policy described in the
158previous section has been agreed by academic partners  and has been
159approved by all industrial participants. This free software policy will
160simplify the definition of the consortium agreement.
161
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