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1\anrdoc{Décrire le contexte économique, social, réglementaire
 dans lequel se
2situe le projet en présentant une analyse des enjeux sociaux, économiques,
3environnementaux, industriels
 Donner si possible des arguments chiffrés, par
4exemple, pertinence et portée du projet par rapport à la demande économique
5(analyse du marché, analyse des tendances), analyse de la concurrence,
6indicateurs de réduction de coûts, perspectives de marchés (champs
7d’application, 
). Indicateurs des gains environnementaux, cycle de vie.}
8
9
10\begin{table}\leavevmode\center
11\begin{small}\begin{tabular}{|l|l|l|l|}\hline
12Segment                 & 2010   & 2011    & 2012 \\\hline\hline
13Communications          & 1,867  & 1,946   & 2,096 \\
14High end                & 467    & 511     & 550 \\\hline
15Consumer                & 550    & 592     & 672 \\
16High end                & 53     & 62      & 75 \\\hline
17Automotive              & 243    & 286     & 358 \\
18High end                & -      & -       & - \\\hline
19Industrial              & 1,102  & 1,228   & 1,406 \\
20High end                & 177    & 188     & 207 \\\hline
21Military/Aereo          & 566    & 636     & 717 \\
22High end                & 56     & 65      & 82 \\\hline\hline
23Total FPGA/PLD          & 4,659  & 5,015   & 5,583 \\
24Total High-End  FPGA    & 753    & 826     & 914 \\\hline
25\end{tabular}\end{small}
26\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
27\end{table}
28%
29Microelectronic components allow the integration of complex functions into products, increases
30commercial attractivity of these products and improves their competitivity.
31Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
32thanks to the developpment of design methodologies and tools for embedded systems.
33Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
34and manufacturing ASICs is very high.
35An IC foundry costs several billions of euros and the fabrication of a specific circuit
36costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
37million USD.
38Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
39volume markets.
40\parlf
41Today, FPGAs become important actors in the computational domain that was originally dominated
42by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
43on a per-application basis. For many applications, FPGAs offer significant performance benefits over
44microprocessors implementation. There is still a performance degradation of one order
45of magnitude versus an equivalent ASIC implementations, but low cost
46(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive
47choice for low-to-medium volume applications.
48Since their introduction in the mid eighties, FPGAs evolved from a simple,
49low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that
50provide a mix of coarse-grained data path units, memory blocks, microprocessor cores,
51on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
52complex systems like multi-processors platform with application dedicated coprocessors.
53Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in
54various application domains. The ``high end'' lines concern only FPGA with high logic
55capacity for complex system implementations.
56This market is in significant expansion and is estimated to 914\,M\$ in 2012.
57%The HPC market size is estimated today by FPGA providers at 214\,M\$.
58%Using FPGA limits the NRE costs to the design cost.
59%This boosts the developpment of automatic design tools and methodologies.
60%
61\parlf
62Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
63Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
64for very high performance (HPC) primes over other requirements. They tend to use the highest
65performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
66architectures and algorithms. These companies show up in different "traditional" applications and market
67segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
68emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
69at 214\,M\$.
70This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
71of FPGA-based solutions is limited by the lack of design automation.
72\\
73\\
74Nowadays, there are no commercial or academic tools covering the whole design flow
75from the system level specification to the bitstream generation neither for embedded system design
76nor for HPC.
77
78%PC => IA et Alain
79%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
80%Je le mets donc en commentaire
81
82%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
83%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
84%processor,  bus core, ...) as well as incorporate their own IP.
85%Designers can then generate a synthesized netlist, simulation test bench and custom
86%software library that reflect the hardware configuration.
87%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
88%simulate the platform at a high design level (systemC).
89%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
90%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
91%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
92%coprocessors from a C++ description.
93%Nevertheless, they can only deal with data dominated applications and they do not handle
94%the platform level.
95%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
96%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
97%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
98%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
99%\xilinx pre-optimized macro-cells.
100%However, this tool targets only DSP based algorithms.
101%\\
102%Consequently, a designer developping an embedded system needs to master four different
103%design environments:
104%\begin{enumerate}
105%  \item a virtual prototyping environment such as SoCLib for system level exploration,
106%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
107%  from \xilinx) to define the hardware architecture,
108%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
109%        coprocessor synthesis,
110%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
111%\end{enumerate}
112%Furthermore, mixing these tools requires an important interfacing effort and this makes
113%the design process very complex and achievable only by designers skilled in many domains.
114
115\begin{center}\begin{minipage}{.9\linewidth}\textit{
116The aim of the COACH project is to integrate all these design steps into a single design framework
117and to allow \textbf{pure software} developpers to design embedded systems.
118}\end{minipage}\end{center}
119
120%PC => IA et Alain
121% le paragraphe suivant est coupé collé de la section suivante 2.2
122
123
124\parlf
125The COACH project proposes an open-source framework for mapping multi-tasks software applications
126on Field Programmable Gate Array circuits (FPGA).
127It aims to propose solutions to the societal/economical challenges by
128providing SMEs novel design capabilities enabling them to increase their
129design productivity with design exploration and synthesis methods that are placed on top
130of the state-of-the-art methods.
131We believe that the combination of a design environment dedicated to software developpers
132and FPGA targets,
133will allow small and even very small companies to propose embedded system and accelerating solutions
134for standard software applications with attractive and competitive prices.
135This new market may explode in the same way as the micro-computer market in the eighties,
136whose success was due to the low cost of the first micro-processors (compared to main frames)
137and the advent of high level programming languages which allowed a high number of programmers
138to launch start-ups in software engineering.
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