source: anr/section-objectif.tex @ 294

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1\anrdoc{\begin{itemize}
2\item Decrire les objectifs du projet et detailler les verrous scientifiques et
3      techniques a lever par la realisation du projet. Insister sur le caractÚre
4          ambitieux et/ou novateur de la proposition.
5\item Decrire eventuellement le ou les produits finaux developpes, presenter les
6      resultats escomptes en proposant si possible des critÚres de reussite et
7      d’evaluation adaptes au type de projet, permettant d’evaluer les resultats en
8      fin de projet.
9\end{itemize}}
10
11% les objectifs scientifiques/techniques du projet.
12The design steps are presented figure~\ref{coach-flow}.
13\ADDED{
14The end-user input is
15either a HPC application (an application running on a PC that must be accelarate),
16or an embedded application (a standalone application),
17or a  sub-system application of a larger design.
18The figure shows that the design flow of embedded and sub-system applications does not differ
19except in the generation step and that the design flow of HPC application just adds a
20preliminary step.
21}
22\begin{figure}[hbtp]\leavevmode\center
23  \includegraphics[width=1.0\linewidth]{flow2}
24  \caption{\label{coach-flow} COACH design flow}
25\end{figure}
26\begin{description}
27\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
28which remains on the PC and the SoC application which is mapped on the FPGA.
29COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC)
30which will allow performance evaluation.
31\item[SoC design:] In this phase,
32COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels.
33The user input will consist of a process network describing the coarse grain parallelism
34of the application, an instance of an architectural template
35and a mapping of processes on the architectural template components.
36COACH will offer different targets to map the processes: 
37software (the process runs as a software task on a SoC processor),
38ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
39and hardware (the process is implemented as a synthesized hardware coprocessor).
40\begin{SUPPRESSEDENV}
41\item[Application compilation:]
42Once the SoC architecture is validated through performances analysis,
43COACH will generate automatically an executable containing the host application and
44the FPGA bitstream. This bitstream contains
45both the hardware architecture and the SoC application software.
46The user will be able to launch the application by
47loading the bitstream on an FPGA and running the executable on PC.
48\end{SUPPRESSEDENV}\begin{ADDEDENV}
49\item[Generation:]
50Once the SoC architecture is validated through performances analysis,
51COACH generates its bitstream in the case of HPC or embedded application,
52or its IP-XACT description for its integration in the case of a sub-system application.
53Both descriptions contain the hardware architecture and the application software.
54Furthermore in the HPC case, an executable containing the host application is
55also generated and the user will be able to launch the application by loading
56the bitstream on an FPGA and running the executable on PC.
57\end{ADDEDENV}
58\end{description}
59 
60% l'avancee scientifique attendue. Preciser l'originalite et le caractere
61% ambitieux du projet.
62%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}
63
64%The main scientific contribution of the project is to unify various synthesis techniques
65%(same input and output formats) allowing the user to swap without engineering effort
66%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
67%Another advantage of this framework is to provide different abstraction levels from
68%a single description.
69%Finally, this description is device family independent and its hardware implementation
70%is automatically generated.
71
72% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
73Hardware/Software co-design is a very complex task. To simplify it, COACH will address the
74following scientific and technological barriers:
75\begin{description}
76\item[\textit{Design Space Exploration by Virtual Prototyping}]:
77    The COACH environment will allow to easily map a parallel application (formally described as
78    an abstract network of process and communication channels) 
79    COACH will permit the system designer to explore the design space, and to define the best
80    hardware/software partitioning of the application.
81\item[\textit{Integration of system level modeling and HLS tools}]:
82    COACH will support the automated generation of hardware accelerators when required
83    by using High-Level Synthesis (HLS) tools. These HLS tools will be
84    fully integrated into a complete system-level design environment.
85    Moreover, COACH will support both data and control dominated applications,
86    and the HLS tools of COACH will support a common language and coding style
87    to avoid re-engineering by the designer.
88    COACH will provide a tool which will automatically explore the micro-architectural
89    design space of coprocessor.
90\item[\textit{High-level code transformation}]:
91    COACH will allow to optimize the memory usage, to enhance the parallelism through
92    loop transformations and parallelization. The challenge is to identify the coarse
93    grained parallelism and to generate,
94    from a sequential algorithm, application containing multiple communicating
95    tasks. COACH will adapt techniques which were developed in the 1990 for
96    the construction of distributed programs. However, in the context of HLS, there are
97    several original problems to be solved, related to the  FIFO communication channels and with
98    memory optimization.
99    COACH will support code transformation by providing a source to source C2C tool.
100\item[\textit{Unified Hardware/Software communication middleware}]:
101    COACH will rely on he SoCLib experience to implement an unified hardware/software communication
102    infrastructure and communication APIs (Application Programming Interface), to support 
103    communications between software tasks running on embedded processors and dedicated
104    hardware coprocessors. The main issue here is to support easy migration
105    from a software implementation to an hardware implementation.
106\item[\textit{Processor customization}]:
107    ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project.
108    COACH will allow system designers to explore the various level of interactions between
109    the original CPU micro-architecture and its extension. It will also allow to retarget
110    the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
111    in a complete System-level design framework.
112\end{description}
113
114%Presenter les resultats escomptes en proposant si possible des criteres de reussite
115%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en
116%fin de projet.
117The main result is the framework. It is composed concretely of:
118a communication middleware for HPC,
1195 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
120Memory optimization HLS and ASIP),
1213 architectural templates that are synthesizable and that can be prototyped,
122one design space exploration tool,
1231 operating systems (DNA/OS).
124\\
125The framework functionalities will be demonstrated with the demonstrators
126(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
127page~\ref{subtask-tutorial}).
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