source: anr/section-objectif.tex @ 318

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1\anrdoc{\begin{itemize}
2\item Decrire les objectifs du projet et detailler les verrous scientifiques et
3      techniques a lever par la realisation du projet. Insister sur le caractÚre
4          ambitieux et/ou novateur de la proposition.
5\item Decrire eventuellement le ou les produits finaux developpes, presenter les
6      resultats escomptes en proposant si possible des critÚres de reussite et
7      d’evaluation adaptes au type de projet, permettant d’evaluer les resultats en
8      fin de projet.
9\end{itemize}}
10
11% les objectifs scientifiques/techniques du projet.
12The design steps are presented figure~\ref{coach-flow}.
13The end-user input is
14either a HPC application (an application running on a PC that must be accelerate),
15or an embedded application (a standalone application),
16or a  sub-system application of a larger design.
17The figure shows that the design flow of embedded and sub-system applications does not differ
18except in the generation step and that the design flow of HPC application just adds a
19preliminary step.
20\begin{figure}[hbtp]\leavevmode\center
21  \includegraphics[width=1.0\linewidth]{flow2}
22  \caption{\label{coach-flow} COACH design flow}
23\end{figure}
24\begin{description}
25\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
26which remains on the PC and the SoC application which is mapped on the FPGA.
27COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC)
28which will allow performance evaluation.
29\item[SoC design:] In this phase,
30COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels.
31The user input will consist of a process network describing the coarse grain parallelism
32of the application, an instance of an architectural template
33and a mapping of processes on the architectural template components.
34COACH will offer different targets to map the processes: 
35software (the process runs as a software task on a SoC processor),
36ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
37and hardware (the process is implemented as a synthesized hardware coprocessor).
38\item[Generation:]
39Once the SoC architecture is validated through performances analysis,
40COACH generates its bitstream in the case of HPC or embedded application,
41or its IP-XACT description for its integration in the case of a sub-system application.
42Both descriptions contain the hardware architecture and the application software.
43Furthermore in the HPC case, an executable containing the host application is
44also generated and the user will be able to launch the application by loading
45the bitstream on an FPGA and running the executable on PC.
46\end{description}
47 
48% l'avancee scientifique attendue. Preciser l'originalite et le caractere
49% ambitieux du projet.
50%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}
51
52%The main scientific contribution of the project is to unify various synthesis techniques
53%(same input and output formats) allowing the user to swap without engineering effort
54%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
55%Another advantage of this framework is to provide different abstraction levels from
56%a single description.
57%Finally, this description is device family independent and its hardware implementation
58%is automatically generated.
59
60% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
61Hardware/Software co-design is a very complex task. To simplify it, COACH will address the
62following scientific and technological barriers:
63\begin{description}
64\item[\textit{Design Space Exploration by Virtual Prototyping}]:
65    The COACH environment will allow to easily map a parallel application (formally described as
66    an abstract network of process and communication channels) 
67    COACH will permit the system designer to explore the design space, and to define the best
68    hardware/software partitioning of the application.
69\item[\textit{Integration of system level modeling and HLS tools}]:
70    COACH will support the automated generation of hardware accelerators when required
71    by using High-Level Synthesis (HLS) tools. These HLS tools will be
72    fully integrated into a complete system-level design environment.
73    Moreover, COACH will support both data and control dominated applications,
74    and the HLS tools of COACH will support a common language and coding style
75    to avoid re-engineering by the designer.
76    COACH will provide a tool which will automatically explore the micro-architectural
77    design space of coprocessor.
78\item[\textit{High-level code transformation}]:
79    COACH will allow to optimize the memory usage, to enhance the parallelism through
80    loop transformations and parallelization. The challenge is to identify the coarse
81    grained parallelism and to generate,
82    from a sequential algorithm, application containing multiple communicating
83    tasks. COACH will adapt techniques which were developed in the 1990 for
84    the construction of distributed programs. However, in the context of HLS, there are
85    several original problems to be solved, related to the  FIFO communication channels and with
86    memory optimization.
87    COACH will support code transformation by providing a source to source C2C tool.
88\item[\textit{Unified Hardware/Software communication middleware}]:
89    COACH will rely on he SoCLib experience to implement an unified hardware/software communication
90    infrastructure and communication APIs (Application Programming Interface), to support 
91    communications between software tasks running on embedded processors and dedicated
92    hardware coprocessors. The main issue here is to support easy migration
93    from a software implementation to an hardware implementation.
94\item[\textit{Processor customization}]:
95    ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project.
96    COACH will allow system designers to explore the various level of interactions between
97    the original CPU micro-architecture and its extension. It will also allow to retarget
98    the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
99    in a complete System-level design framework.
100\end{description}
101
102%Presenter les resultats escomptes en proposant si possible des criteres de reussite
103%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en
104%fin de projet.
105The main result is the framework. It is composed concretely of:
106a communication middleware for HPC,
1075 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
108Memory optimization HLS and ASIP),
1093 architectural templates that are synthesizable and that can be prototyped,
110one design space exploration tool,
1111 operating systems (DNA/OS).
112\\
113The framework functionalities will be demonstrated with the demonstrators
114(see task-7 page~\pageref{task-demonstrator}) and the tutorial example (see task-8
115page~\pageref{subtask-tutorial}).
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