source: anr/section-position.tex @ 297

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1\anrdoc{Preciser:\begin{itemize}
2\item positionnement du projet par rapport au contexte developpe precedemment :
3          vis- a-vis des projets et recherches concurrents, complementaires ou
4          anterieurs, des brevets et standards...
5\item indiquer si le projet s'inscrit dans la continuite de projet(s) anterieurs
6          deja finances par l'ANR. Dans ce cas, presenter brievement les resultats acquis,
7\item positionnement du projet par rapport aux axes thematiques de l'appel a projets,
8\item positionnement du projet aux niveaux europeen et international.
9\end{itemize}}
10
11% Relevance of the proposal
12%The COACH proposal addresses directly the \emph{Embedded Systems} item of
13%the ARPEGE program.
14
15%PC => IA et ALain
16%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1
17
18%It aims to propose solutions to the societal/economical challenges by
19%providing SMEs novel design capabilities enabling them to increase their
20%design productivity with design exploration and synthesis methods that are placed on top
21%of the state-of-the-art methods.
22%This project proposes an open-source framework for mapping multi-tasks software applications
23%on Field Programmable Gate Array circuits (FPGA).
24%%%
25\parlf
26COACH will contribute to build an open design and run-time
27environment, including communication middleware and tools to support
28developers in the production of embedded software, through all phases of the software lifecycle,
29from requirements analysis downto deployment and maintenance.
30More specifically, COACH focuses on:
31\begin{itemize}
32\item High level methods and concepts (esp. requirements and architectural level) for system
33design, development and integration, addressing complexity aspects and modularity.
34\item Open and modular design environments, enabling flexibility and extensibility by
35means of new or sector-specific tools and ensuring consistency and traceability along the
36development lifecycle.
37\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
38environment, suitable for co-operative and distributed development.
39\item \mustbecompleted{IP-XACT: .... MAGILLEM...}
40\end{itemize}
41COACH outcome will contribute to strengthen Europe's competitive position by developing
42technologies and methodologies for product design, focusing (in compliance with the
43%scope of the above program) on technologies, engineering methodologies, novel tools,
44%methods which facilitate resource use efficiency. The approaches and tools to be developed
45%in COACH will enable new and emerging information technologies for the development,
46%methods which facilitate resource use efficiency. The COACH approaches and tools
47scope of the above program) on technologies, engineering methodologies, novel tools
48which facilitate resource use efficiency. The COACH approaches and tools
49will enable new and emerging information technologies for the development,
50manufacturing and integration of devices and related software into end-products.
51%%%
52\parlf\noindent
53The COACH project will benefit from a number of previous recent projects:
54\begin{description}
55  \item[SOCLIB]
56    The SoCLib ANR platform (2007-2009) is an open infrastructure
57    that supports system level virtual prototyping of shared memory, multi-processors
58    architectures, and provides tools to map multi-tasks software application on these
59    architectures, for reliable performance evaluation.
60    The core of this platform is a library of SystemC simulation models for
61    general purpose IP cores.
62    It provides also embedded operating systems and software/hardware
63    communication middleware.
64  \item[ROMA] The ROMA ANR project \cite{roma}
65    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
66    proposes to develop a reconfigurable processor, exhibiting high
67    silicon density and power efficiency, able to adapt its computing
68    structure to computation patterns that can be speed-up and/or
69    power efficient.  %The ROMA project study a pipeline of
70    %evolved low-power coarse grain reconfigurable operators to avoid
71    %traditional overhead, in reconfigurable devices, related to the
72    %interconnection network. 
73        The project will borrow from the ROMA
74    ANR project and the ongoing joint INRIA-STMicro
75    Nano2012 project to adapt existing pattern extraction algorithms
76    and datapath merging techniques to ASIP synthesis.
77%    and datapath merging techniques to the synthesis of customized
78%    ASIP processors.
79  \item[TSAR]
80     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a
81%    The TSAR MEDEA+ project (2008-2010) targets the design of a
82    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
83    plaform for virtual prototyping. COACH will benefit from the synthesizable VHDL
84    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
85  \item[BioWic]
86    On the HPC application side, we also hope to benefit from the experience in
87    hardware acceleration of bioinformatic algorithms/workfows gathered by the
88    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
89    be able to validate the framework on real-life HPC applications.
90  \item[SoCket]  \mustbecompleted{...... MAGILEM ......}
91  \item[HOSPI]   \mustbecompleted{...... MAGILEM ......}
92  \item[SoftSoc] \mustbecompleted{...... MAGILEM ......}
93\end{description}
94%%%
95\parlf\noindent
96The partners involved in the COACH project have a well established expertise
97in the following domains:
98\begin{itemize}
99  \item 
100    In the field of High Level Synthesis (HLS), the project
101    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
102    developed by the \ubs laboratory, and with the UGH~\cite{ugh08} project developed
103    by the \upmc and \tima laboratories.
104  \item
105    Regarding system level architecture, the project is based on the know-how
106    acquired by \upmc and \tima in the framework of various projects 
107    in the field of communication architectures for shared memory multi-processors systems
108    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
109    As an example, the DSPIN project is now used in the TSAR project.
110  \item
111    Regarding Application Specific Instruction Processor (ASIP) design, the
112    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
113    expertise in the domain of retargetable compiler
114    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
115    compilers~\cite{ASAP05} since 2002).
116  \item
117    In the field of compilers, the \lip Compsys group was founded in 2002
118    by several senior researchers with experience in
119    high performance computing and automatic parallelization. They have been
120    among the initiators of the polyhedral model, a theory which serve to
121    unify many parallelism detection and exploitation techniques for regular
122    programs. It is expected that the techniques developped by \lip for
123    parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb},
124    process construction \cite{Feau:96} and memory management \cite{bee}
125    will be very useful as a front-end for HLS tools.
126  \item
127    Regarding \mustbecompleted{.... MAGILLEM ... IP-XACT}
128\end{itemize}
129%%%
130\parlf\noindent
131The COACH project totally fulfills the objectives of the axis 2 "METHODES,
132OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES".
133\mustbecompleted{BEGIN-FIXME}
134COACH will address new embedded systems architectures by allowing the design of
135Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
136constraints and objectives (real-time, low-power). It will permit designing  complex SoC
137based on IP cores (memory, peripherals...),
138running Embedded Software, as well as an Operating System with associated middleware and
139API and using hardware accelerator automatically generated. It will also permit to use
140efficiently different dynamic system management techniques and re-configuration mechanisms.
141\\
142COACH will address High-Performance Computing (HPC) by helping designers to accelerate an
143application running on a PC.
144By providing tools that translate high level language programs to FPGA
145configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the
146PC bus (through a communication link like PCI/X).
147\mustbecompleted{END-FIXME}
148\parlf
149The COACH project well fits also the axis 5 "USAGES".
150\mustbecompleted{BEGIN-FIXME}
151COACH will address robotic and control applications by
152allowing to design complex systems based on MPSoC architecture.
153Like in the consumer electronics domain, future control applications
154will employ more and more SoC for safety and security applications.
155Application domains for such systems are for example automotive
156or avionics domains (e.g. collision-detection, intelligent navigation...).
157Manufacturing technology will also increasingly need high-end vision analysis and high-speed
158robot control.
159%
160The results of the COACH project will help users to build cryptographic secure systems implemented in
161hardware or both in software/hardware in an effective way, substantially enhancing the
162process productivity of the cryptographic algorithms hardware synthesis, improving the
163quality and reducing the design time and the cost of synthesised cryptographic devices.
164\mustbecompleted{END-FIXME}
165\parlf
166Finally, it is worth to note that this project covers priorities defined by the commission
167experts in the field of Information Technolgies Society (IST) for Embedded
168Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity
169and allowing to apply efficiently applications and various products on embedded platforms,
170considering resources constraints (delays, power, memory, etc.), security and quality
171services$>>$}.
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