source: anr/section-position.tex @ 322

Last change on this file since 322 was 319, checked in by coach, 14 years ago

template for Christophe CV, minor language modifications

anr/annexe-cv.tex
anr/section-consortium-people.tex
anr/section-objectif.tex
anr/section-1.tex
anr/section-2.tex
anr/section-position.tex
anr/section-etat-de-art.tex
anr/section-issues.tex

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1\anrdoc{Preciser:\begin{itemize}
2\item positionnement du projet par rapport au contexte developpe precedemment :
3          vis- a-vis des projets et recherches concurrents, complementaires ou
4          anterieurs, des brevets et standards...
5\item indiquer si le projet s'inscrit dans la continuite de projet(s) anterieurs
6          deja finances par l'ANR. Dans ce cas, presenter brievement les resultats acquis,
7\item positionnement du projet par rapport aux axes thematiques de l'appel a projets,
8\item positionnement du projet aux niveaux europeen et international.
9\end{itemize}}
10
11% Relevance of the proposal
12%The COACH proposal addresses directly the \emph{Embedded Systems} item of
13%the ARPEGE program.
14
15%PC => IA et ALain
16%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1
17
18%It aims to propose solutions to the societal/economical challenges by
19%providing SMEs novel design capabilities enabling them to increase their
20%design productivity with design exploration and synthesis methods that are placed on top
21%of the state-of-the-art methods.
22%This project proposes an open-source framework for mapping multi-tasks software applications
23%on Field Programmable Gate Array circuits (FPGA).
24%%%
25\subsubsection*{Positionning in regards with the economical and social context}
26COACH will contribute to build an open design and run-time
27environment, including communication middleware and tools to support
28developers in the production of embedded software, through all phases of the software lifecycle,
29from requirements analysis down to deployment and maintenance.
30More specifically, COACH focuses on:
31\begin{itemize}
32\item High level methods and concepts (esp. requirements and architectural level) for system
33design, development and integration, addressing complexity aspects and modularity.
34\item Open and modular design environments, enabling flexibility and extensibility by
35means of new or sector-specific tools and ensuring consistency and traceability along the
36development lifecycle.
37\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
38environment, suitable for co-operative and distributed development.
39\item Integration of the solutions and engines being developped into a state of the art SoC and system
40design flow, using the IP-XACT IEEE 1685 standard
41\end{itemize}
42COACH outcome will contribute to strengthen Europe's competitive position by developing
43technologies and methodologies for product design, focusing (in compliance with the
44%scope of the above program) on technologies, engineering methodologies, novel tools,
45%methods which facilitate resource use efficiency. The approaches and tools to be developed
46%in COACH will enable new and emerging information technologies for the development,
47%methods which facilitate resource use efficiency. The COACH approaches and tools
48scope of the above program) on technologies, engineering methodologies, novel tools
49which facilitate resource use efficiency. The COACH approaches and tools
50will enable new and emerging information technologies for the development,
51manufacturing and integration of devices and related software into end-products.
52%%%
53\parlf\noindent
54\subsubsection*{Positionning and continuity with other projects}
55The COACH project will benefit from a number of previous recent projects:
56\begin{description}
57  \item[SOCLIB]
58    The SoCLib ANR platform (2007-2009) is an open infrastructure
59    that supports system level virtual prototyping of shared memory, multi-processors
60    architectures, and provides tools to map multi-tasks software application on these
61    architectures, for reliable performance evaluation.
62    The core of this platform is a library of SystemC simulation models for
63    general purpose IP cores.
64    It provides also embedded operating systems and software/hardware
65    communication middleware.
66  \item[ROMA] The ROMA ANR project \cite{roma}
67    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
68    proposes to develop a reconfigurable processor, exhibiting high
69    silicon density and power efficiency, able to adapt its computing
70    structure to computation patterns that can be speed-up and/or
71    power efficient.  %The ROMA project study a pipeline of
72    %evolved low-power coarse grain reconfigurable operators to avoid
73    %traditional overhead, in reconfigurable devices, related to the
74    %interconnection network. 
75        The project will borrow from the ROMA
76    ANR project and the ongoing joint INRIA-STMicro
77    Nano2012 project to adapt existing pattern extraction algorithms
78    and datapath merging techniques to ASIP synthesis.
79%    and datapath merging techniques to the synthesis of customized
80%    ASIP processors.
81  \item[TSAR]
82     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a
83%    The TSAR MEDEA+ project (2008-2010) targets the design of a
84    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
85    plaform for virtual prototyping. COACH will benefit from the synthesizable VHDL
86    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
87  \item[BioWic]
88    On the HPC application side, we also hope to benefit from the experience in
89    hardware acceleration of bioinformatic algorithms/workfows gathered by the
90    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
91    be able to validate the framework on real-life HPC applications.
92
93  \item[SoCket] 
94    The design flow defined in this project targets the design of critical embedded systems.
95    It covers important steps as system architecture exploration, and the definition of virtual
96    prototypes at different levels of abstraction to support early embedded software development,
97    verification of hardware blocks, and preparation of certification activities.
98    COACH solutions and engines will be specified to be integrated into this standard flow.
99    MDS, Thales TRT, TIMA are already collaborating in this project.
100
101  \item[HOSPI] 
102     The objective of this project (with TIMA and MDS) was to define innovative methods, and implement the associated tools, to ease
103     the mapping of data-streaming applications on heterogeneous platforms. COACH will use the abstracted description
104     format based on IP-XACT for hardware platforms and the results concerning the integration of code generators into a standard design flow.
105
106  \item[SoftSoC] 
107     TIMA and MDS are involved in this project, which aims at the standard definition and generation of Hardware Dependent Software layers of a system.
108     Crucial extensions of the IP-XACT standard will be reused from this project, as well as code generation techniques based on them. 
109
110\end{description}
111%%%
112\parlf\noindent
113The partners involved in the COACH project have a well established expertise
114in the following domains:
115\begin{itemize}
116  \item 
117    In the field of High Level Synthesis (HLS), the project
118    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
119    developed by the \ubs laboratory, and with the UGH~\cite{ugh08} project developed
120    by the \upmc and \tima laboratories.
121  \item
122    Regarding system level architecture, the project is based on the know-how
123    acquired by \upmc and \tima in the framework of various projects 
124    in the field of communication architectures for shared memory multi-processors systems
125    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
126    As an example, the DSPIN project is now used in the TSAR project.
127  \item
128    Regarding Application Specific Instruction Processor (ASIP) design, the
129    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
130    expertise in the domain of retargetable compiler
131    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
132    compilers~\cite{ASAP05} since 2002).
133  \item
134    In the field of compilers, the \lip Compsys group was founded in 2002
135    by several senior researchers with experience in
136    high performance computing and automatic parallelization. They have been
137    among the initiators of the polyhedral model, a theory which serve to
138    unify many parallelism detection and exploitation techniques for regular
139    programs. It is expected that the techniques developped by \lip for
140    parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb},
141    process construction \cite{Feau:96} and memory management \cite{bee}
142    will be very useful as a front-end for HLS tools.
143  \item
144    Regarding industrial flow integration \mds will bring its strong expertise
145    in IEEE 1685 (IP-XACT) standard. \mds team is involved and contributes actively
146    to it since 2003 and Magillem tool suite is used for its validation. Magillem is used in
147    industrial production flows of ST, NXP, TI, Qualcomm, and system integrators like Thales,
148    Astrium, Thomson, etc. This guarantees a strong alignement on customers needs and enhanced results exploitation.
149
150\end{itemize}
151%%%
152\subsubsection*{Relevance to the call axis}
153This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing
154methods and tools for the design of application to be run on platforms of the next generation. Results will be gained in term of productivity,
155time-to-market (automation and code generation) and safety (management of high level sepcifications down to implementation).
156In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES,
157OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES".
158COACH will address new embedded systems architectures by allowing the design of
159Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
160constraints and objectives (real-time, low-power). It will permit designing  complex SoC
161based on IP cores (memory, peripherals...),
162running Embedded Software, as well as an Operating System with associated middleware and
163API and using automatically generated hardware accelerators. It will also permit to use
164efficiently different dynamic system management techniques and re-configuration mechanisms.
165The results will be tailored in order to be integrated in standard design flow of critical systems.
166\\
167COACH will address High-Performance Computing (HPC) by helping designers to accelerate an
168application running on a PC.
169By providing tools that translate high level language programs to FPGA
170configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the
171PC bus (through a communication link like PCI/X).
172\parlf
173The COACH project has been also shaped to answer to the axis 5 "USAGES".
174COACH will address robotic and control applications by
175allowing to design complex systems based on MPSoC architecture.
176Like in the consumer electronics domain, future control applications
177will employ more and more SoC for safety and security applications.
178Application domains for such systems are for example automotive
179or avionics domains (e.g. collision-detection, intelligent navigation...).
180Manufacturing technology will also increasingly need high-end vision analysis and high-speed
181robot control.
182%
183The results of the COACH project will help users to build cryptographic secure systems implemented in
184hardware or both in software/hardware in an effective way, substantially enhancing the
185process productivity of the cryptographic algorithms hardware synthesis, improving the
186quality and reducing the design time and the cost of synthesised cryptographic devices.
187%
188\subsubsection*{European and international positionning}
189%
190Finally, it is worth to note that this project covers priorities defined by the commission
191experts in the field of Information Technolgies Society (IST) for Embedded
192Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity
193and allowing to apply efficiently applications and various products on embedded platforms,
194considering resources constraints (delays, power, memory, etc.), security and quality
195services$>>$}.
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