\anrdoc{Preciser:\begin{itemize} \item positionnement du projet par rapport au contexte developpe precedemment : vis- a-vis des projets et recherches concurrents, complementaires ou anterieurs, des brevets et standards... \item indiquer si le projet s'inscrit dans la continuite de projet(s) anterieurs deja finances par l'ANR. Dans ce cas, presenter brievement les resultats acquis, \item positionnement du projet par rapport aux axes thematiques de l'appel a projets, \item positionnement du projet aux niveaux europeen et international. \end{itemize}} % Relevance of the proposal %The COACH proposal addresses directly the \emph{Embedded Systems} item of %the ARPEGE program. %PC => IA et ALain %J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1 %It aims to propose solutions to the societal/economical challenges by %providing SMEs novel design capabilities enabling them to increase their %design productivity with design exploration and synthesis methods that are placed on top %of the state-of-the-art methods. %This project proposes an open-source framework for mapping multi-tasks software applications %on Field Programmable Gate Array circuits (FPGA). %%% \subsubsection*{Positioning in regards with the economical and social context} COACH will contribute to build an open design and run-time environment, including communication middleware and tools to support developers in the production of embedded software, through all phases of the software life cycle, from requirements analysis down to deployment and maintenance. More specifically, COACH focuses on: \begin{itemize} \item High level methods and concepts (esp. eequirements and architectural level) for system design, development and integration, addressing complexity aspects and modularity. \item Open and modular design environments, enabling flexibility and extensibility by means of new or sector-specific tools and ensuring consistency and traceability along the development life cycle. \item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive environment, suitable for co-operative and distributed development. \item Integration of the solutions and engines being developed into a state of the art SoC and system design flow, using the IP-XACT IEEE 1685 specification. \end{itemize} The COACH results will contribute to strengthen Europe's competitive position by developing technologies and methodologies for product design, focusing (in compliance with the %scope of the above program) on technologies, engineering methodologies, novel tools, %methods which facilitate resource use efficiency. The approaches and tools to be developed %in COACH will enable new and emerging information technologies for the development, %methods which facilitate resource use efficiency. The COACH approaches and tools scope of the above program) on technologies, engineering methodologies, novel tools which facilitate resource use efficiency. The COACH approaches and tools will enable new and emerging information technologies for the development, manufacturing and integration of devices and related software into end-products. %%% \subsubsection*{Positioning and continuity with other projects} The COACH project will benefit from a number of previous recent projects: \begin{description} \item[SOCLIB] The SoCLib ANR platform (2007-2009) is an open infrastructure that supports system level virtual prototyping of shared memory, multi-processors architectures, and provides tools to map multi-tasks software application on these architectures, for reliable performance evaluation. The core of this platform is a library of SystemC simulation models for general purpose IP cores. It provides also embedded operating systems and software/hardware communication middleware. \item[ROMA] The ROMA ANR project (2007-2010) \cite{roma,RAFFIN:2010:INRIA-00539874:1} involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D, proposes to develop a reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its computing structure to computation patterns that can be faster or more power efficient. %The ROMA project study a pipeline of %evolved low-power coarse grain reconfigurable operators to avoid %traditional overhead, in reconfigurable devices, related to the %interconnection network. The project will borrow from the ROMA ANR project and the ongoing joint INRIA-STMicro Nano2012 project to adapt existing pattern extraction algorithms and datapath merging techniques to ASIP synthesis. % and datapath merging techniques to the synthesis of customized % ASIP processors. \item[TSAR] The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a % The TSAR MEDEA+ project (2008-2010) targets the design of a scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib platform for virtual prototyping. COACH will benefit from the synthesizable VHDL models developed in the framework of TSAR (MIPS32 processor core, and RING interconnect). \item[BioWic] On the HPC application side, we also hope to benefit from the experience in hardware acceleration of bioinformatic algorithms/workfows gathered by the CAIRN group (ANR BioWic project 2009-2011), so as to be able to validate the framework on real-life HPC applications. \item[SoCket] The design flow defined in this project targets the design of critical embedded systems. It covers important steps as system architecture exploration, and the definition of virtual prototypes at different levels of abstraction to support early embedded software development, verification of hardware blocks, and preparation of certification activities. COACH solutions and engines will be specified to be integrated into this standard flow. MDS, Thales TRT, TIMA are already collaborating in this project. \item[HOSPI] The objective of this project (with TIMA and MDS) was to define innovative methods, and implement the associated tools, to ease the mapping of data-streaming applications on heterogeneous platforms. COACH will use the abstracted description format based on IP-XACT for hardware platforms and the results concerning the integration of code generators into a standard design flow. \item[SoftSoC] TIMA and MDS are involved in this project which aims at the definition and generation of Hardware Dependent Software layers of a system. Crucial extensions of the IP-XACT standard will be reused from this project, as well as code generation techniques based on them. \end{description} %%% The partners involved in the COACH project have a well established expertise in the following domains: \begin{itemize} \item In the field of High Level Synthesis (HLS), the project leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project developed by the \ubs laboratory, and with the UGH~\cite{ugh08} project developed by the \upmc and \tima laboratories. \item Regarding system level architecture, the project is based on the know-how acquired by \upmc and \tima in the framework of various projects in the field of communication architectures for shared memory multi-processors systems (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA). As an example, the DSPIN project is now used in the TSAR project. \item Regarding Application Specific Instruction Processor (ASIP) design, the CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of expertise in the domain of retargetable compiler (Armor/Calife~\cite{CODES99} since 1996, and the Gecos compilers~\cite{ASAP05} since 2002). \item In the field of compilers, the \lip Compsys group was founded in 2002 by several senior researchers with experience in high performance computing and automatic parallelization. They have been among the initiators of the polyhedral model, a theory which serve to unify many parallelism detection and exploitation techniques for regular programs. It is expected that the techniques developed by \lip for parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb}, process construction \cite{Feau:96} and memory management \cite{bee} will be very useful as a front-end for HLS tools. \item Regarding industrial flow integration \mds will bring its strong expertise in IEEE 1685 (IP-XACT) standard. The \mds team is involved and contributes actively to it since 2003 and the Magillem tool suite is used for its validation. Magillem is used in industrial production flows of ST, NXP, TI, Qualcomm, and system integrators like Thales, Astrium, Thomson, etc. This guarantees a strong alignement on customers needs and enhanced results exploitation. \end{itemize} %%% \subsubsection*{Relevance to the call axis} This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing methods and tools for the design of application to be run on platforms of the next generation. Improvements can be expected for productivity, time-to-market (automation and code generation) and reliability (management of high level specifications down to implementation). In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES, OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES". COACH will address new embedded systems architectures by allowing the design of Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design constraints and objectives (real-time, low-power). It will permit designing complex SoC based on IP cores (memory, peripherals...), running Embedded Software, as well as an Operating System with associated middleware and API and using automatically generated hardware accelerators. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms. The results will be tailored in order to be integrated in standard design flow of critical systems. \\ COACH will address High-Performance Computing (HPC) by helping designers to accelerate an application running on a PC. By providing tools that translate high level language programs to FPGA configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the PC bus (through a communication link like PCI/X). \parlf The COACH project has been also shaped to answer to the axis 5 "USAGES". COACH will address robotic and control applications by allowing to design complex systems based on MPSoC architecture. Like in the consumer electronics domain, future control applications will employ more and more SoC for safety and security applications. Application domains for such systems are for example automotive or avionics domains (e.g. collision-detection, intelligent navigation...). Manufacturing technology will also increasingly need high-end vision analysis and high-speed robot control. % The results of the COACH project will help users to build cryptographic secure systems implemented in in a combination of hardware and software in an effective way, substantially enhancing the productivity of the field, improving the quality and reducing the design time and the cost of synthesised cryptographic devices. % COACH will contribute to enhance the safety in design of critical system for two main reasons: \begin{itemize} \item by providing a way to automate the mapping of application onto MPSoC architecture; code generators of the tool chain will be subject to certification. \item by relaying on design flow defined by SoCKET, which is dedicated to safety of critical systems, COACH will benefit from features related to requirements traceability. \end{itemize} % \subsubsection*{European and international positioning} % Finally, it is worth noting that this project covers priorities defined by the commission experts in the field of Information Technologies Society (IST) for Embedded Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity and allowing to apply efficiently applications and various products on embedded platforms, considering resources constraints (delays, power, memory, etc.), security and quality services$>>$}.