source: anr/section-project-task-schedule.tex @ 299

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1\anrdoc{\begin{itemize}
2\item Presenter sous forme graphique un echeancier des differentes taches
3et leurs dependances (diagramme de Gantt par exemple).
4\item Presenter un tableau synthetique  de l'ensemble des livrables du
5projet (numero de tache, date, intitule, responsable).
6\item Preciser de facon synthetique les jalons scientifiques et/ou
7techniques, les principaux points de rendez-vous, les points bloquants ou
8aleas qui risquent de remettre en cause l'aboutissement du projet ainsi que
9les reunions de projet prevues.\end{itemize}}
10
11\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90}
12\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99}
13\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7}
14\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7}
15\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4}
16\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24}
17\def\ganttlabelstyle#1{\begin{small}#1\end{small}}
18\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}}
19
20\begin{figure}\leavevmode\center
21\hspace*{-.6cm}
22\input{gantt.tex}
23\caption{\label{gantt}Gantt diagram of deliverables}
24\end{figure}
25
26%\begin{figure}\leavevmode\center
27%\hspace*{-.4cm}%\vspace{-1.5cm}
28%\input{gantt1.tex}
29%\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-6)}
30%\end{figure}
31%
32%\begin{figure}\leavevmode\center
33%\hspace*{-.4cm}%\vspace{-1.5cm}
34%\input{gantt2.tex}
35%\caption{\label{gantt2}Gantt diagram of deliverables (task-7 and task-8)}
36%\end{figure}
37
38The figure~\ref{gantt} presents the Gantt diagram of the project.
39%The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project.
40Before the final release (T0+36), there are 4 milestones (red lines on the figures) at
41$T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent
42deliverables.
43\begin{description}
44\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of
45    the demonstatrors as a reference software.
46\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are
47    written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
48    The main restrictions are:
49    1) Only the neutral architectural template is supported,
50    2) HAS is not available (but prototyping with virtual coprocessors is available),
51    3) Enhanced communication schemes are not available.
52    4) ASIP compilation flow is not available.
53\item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
54    features are availables. A preliminary version of the ASIP synthesis flow is supported, for a
55   simple extensible MIPS model. The main restriction is that COACH can not yet
56   generate FPGA-SoC for \altera and \xilinx architectural templates.
57    The others restriction is that the HAS tools are not yet fully operational.
58\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
59    supported.
60    The main restriction are:
61    1) The backend HAS tools have not been yet enhanced,
62    2) Dynamic partial reconfiguration is not supported,
63    3) NIOS processor instruction set extension is supported, but only for user specified patterns.
64\item[Final Release ($T0+36$)] 
65       
66\end{description}
67This organisation allows the project to globally progress step by step mixing development
68and demonstrator deliverables.
69Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
70at the integration phase is significantly reduced.
71\par
72The risks that have been identified at the beginning of the project are the following:
73\begin{description}
74\item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})]
75        Partners have to agree on a convenient exchange format for all tools involved.
76        Because all the HAS tools rely on it, the \xcoach format specification is a
77    crucial step. There are no work-around but as mentionned in
78    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it
79        for a full year and a preliminary document already exists.
80%\item[\xcoachplus format (\novers{\specXcoachDoc},
81%      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
82%    Its aim is the generation of the coprocessors (hardware \& prototyping model).
83%    By centralizing the coprocessor generation, it guarantees their functioning
84%    independently of the used HAS tools.
85%       Our experience with UGH and GAUT give us confidence in the succes of this
86%       task.
87\item[Virtual prototyping of \altera \& \xilinx architectural templates ({\NOVERScsgImplementation})]
88     The SoCLib component library contains several SystemC models used for the virtual
89     prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).
90     Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
91     If the workload of this simulation model development is too important, virtual prototyping
92         of those architectural templates will not be directly supported.
93         The three architectural templates being quite similar, the virtual
94         prototyping will use the neutral architectural template.
95\item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
96     If one of these tasks is impossible or too important or leads to inefficiency,
97     it will be abandoned.
98     In this case, the neutral architectural template will not be available for HPC and
99     a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
100     virtual prototyping.
101\end{description}
102\parlf
103Finally the list of all the deliverables is presented on figure~\ref{all-delivrables}.
104\begin{figure}\leavevmode\center
105{
106\fontsize{7pt}{9pt}\selectfont
107\settowidth\desclen{XILINX RTL optimisation (5)}
108\def\Sformat#1{\textsc{#1}}
109%\hspace*{-2.5mm}
110\begin{minipage}{1.0\linewidth}
111\input{table_livrable_01.tex}
112\hfill\hspace*{1mm}\hfill
113\input{table_livrable_02.tex}
114\end{minipage}
115}
116\caption{\label{all-delivrables}All the deliverables}
117\end{figure}
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