source: anr/section-project-task-schedule.tex @ 355

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1\anrdoc{\begin{itemize}
2\item Presenter sous forme graphique un echeancier des differentes taches
3et leurs dependances (diagramme de Gantt par exemple).
4\item Presenter un tableau synthetique  de l'ensemble des livrables du
5projet (numero de tache, date, intitule, responsable).
6\item Preciser de facon synthetique les jalons scientifiques et/ou
7techniques, les principaux points de rendez-vous, les points bloquants ou
8aleas qui risquent de remettre en cause l'aboutissement du projet ainsi que
9les reunions de projet prevues.\end{itemize}}
10
11\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90}
12\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99}
13\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7}
14\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7}
15\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4}
16\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=27}
17%\def\ganttlabelstyle#1{\begin{small}#1\end{small}}
18\def\ganttlabelstyle#1{\begin{small}\hyperlink{#1}{#1}\end{small}}
19\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}}
20
21\begin{figure}\leavevmode\center
22\hypersetup{
23    %backref=true,
24    %pagebackref=true,
25    %hyperindex=true,
26    colorlinks=true, %colorise les liens
27    breaklinks=true, %permet le retour à la ligne dans les lien
28    urlcolor= blue,  %couleur des hyperliens
29    linkcolor= black  %couleur des liens internes
30}
31\hspace*{-.6cm}
32\input{gantt.tex}
33\caption{\label{gantt}Gantt diagram of deliverables}
34\end{figure}
35
36%\begin{figure}\leavevmode\center
37%\hspace*{-.4cm}%\vspace{-1.5cm}
38%\input{gantt1.tex}
39%\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-6)}
40%\end{figure}
41%
42%\begin{figure}\leavevmode\center
43%\hspace*{-.4cm}%\vspace{-1.5cm}
44%\input{gantt2.tex}
45%\caption{\label{gantt2}Gantt diagram of deliverables (task-7 and task-8)}
46%\end{figure}
47
48The figure~\ref{gantt} presents the Gantt diagram of the project.
49%The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project.
50Before the final release (T0+36), there are 4 milestones (red lines on the figures) at
51$T0+6$, $T0+12$, $T0+18$ and $T0+27$ that are rendez-vous points of the precedent
52deliverables.
53\begin{description}
54  \item[Milestone 1 ($T0+6$)]
55    Specification of COACH inputs, of the \xcoach format and of
56    the demonstatrors as a reference software.
57  \item[Milestone 2 ($T0+12$)]
58    The first COACH release. At this step the demonstrators are
59    written in the COACH input format. This COACH release allows to prototype
60    and to generate the FPGA-SoC.
61    The main restrictions are:
62    1) Only the neutral architectural template is supported,
63    2) HAS is not available (but prototyping with virtual coprocessors is available),
64    3) Enhanced communication schemes are not available.
65    4) ASIP compilation flow is not available.
66  \item[Milestone 3 ($T0+18$)]
67    The second COACH release. At this step most of the COACH features are available.
68    A preliminary version of the ASIP synthesis flow is supported, for a
69    simple extensible MIPS model. The main restriction is that COACH can not yet
70    generate FPGA-SoC for \altera and \xilinx architectural templates.
71    The others restriction is that the HAS tools are not yet fully operational.
72\item[Milestone 4 ($T0+27$)]
73    The pre-release of the COACH project. The full design flow is supported.
74    The main restrictions are:
75    1) Automatic frequency calibration of coprocessor is not available.
76    2) Automatic HPC set up is not yet available.
77    3) NIOS processor instruction set extension is supported, but only for user
78    specified patterns.
79    4) GAUT enhancements are not available.
80\item[Final Release ($T0+36$)] 
81
82\end{description}
83This organisation allows the project to globally progress step by step mixing
84development and demonstrator deliverables.
85Hence, demonstrator feed-back will arrive early and so the risk to point out
86incompatibility at the integration phase is significantly reduced.
87\par
88The risks that have been identified at the beginning of the project are the following:
89\begin{description}
90  \item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})]
91    Partners have to agree on a convenient exchange format for all tools involved.
92    Because all the HAS tools rely on it, the \xcoach format specification is a
93    crucial step.
94    There are no work-around but as mentionned in section~\ref{xcoach-problem}
95    (page~\pageref{xcoach-problem}) the five academic partners have worked on it
96    for a full year and a preliminary document already exists.
97%\item[\xcoachplus format (\novers{\specXcoachDoc},
98%      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
99%    Its aim is the generation of the coprocessors (hardware \& prototyping model).
100%    By centralizing the coprocessor generation, it guarantees their functioning
101%    independently of the used HAS tools.
102%   Our experience with UGH and GAUT give us confidence in the succes of this
103%   task.
104  \item[Virtual prototyping  ({\NOVERScsgImplementation})]
105    In this project, only the virtual prototyping of the neutral architectural
106    template is supported.
107    We think that this restriction is not a serious problem.
108    Indeed the \altera \& \xilinx architectural templates being architecturally close of
109    the neutral architectural template, an efficient software/hardware partition
110    on the neutral architectural template is also an efficient on the other
111    architectural templates.
112    The project will allow an experimental verification of this assumption.
113%  \item[Virtual prototyping of \altera \& \xilinx architectural templates
114%    ({\NOVERScsgImplementation})]
115%    The SoCLib component library contains several SystemC models used for the
116%    virtual prototyping of the \altera and \xilinx architectural templates
117%    (NIOS and \xilinxcpu processor cores).
118%    Nevertheless, at this time we do not know how many IP cores SystemC
119%    simulation models have to be developped.
120%    If the workload of this simulation model development is too important,
121%    virtual prototyping of those architectural templates will not be directly
122%    supported.
123%    The three architectural templates being quite similar, the virtual
124%    prototyping will use the neutral architectural template.
125  \item[VCI/AVALON \& VCI/\xilinxbus bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
126    These bridges may decrease the efficiency of the \altera \& \xilinx
127    architectural templates.
128    Developing the communication components (MWMR) for the AVALON and \xilinxbus buses
129    will correct this problem.
130%    If one of these tasks is impossible or too important or leads to inefficiency,
131%    it will be abandoned.
132%    In this case, the neutral architectural template will not be available for HPC and
133%    a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
134%    virtual prototyping.
135\end{description}
136\parlf
137Finally the list of all the deliverables is presented on figure~\ref{all-delivrables}.
138\begin{figure}[t]\leavevmode\center
139{
140\fontsize{7pt}{9pt}\selectfont
141\settowidth\desclen{XILINX RTL optimisation (5)}
142\def\Sformat#1{\textsc{#1}}
143%\hspace*{-2.5mm}
144\begin{minipage}{1.0\linewidth}
145\input{table_livrable_01.tex}
146\hfill\hspace*{1mm}\hfill
147\input{table_livrable_02.tex}
148\end{minipage}
149}
150\caption{\label{all-delivrables}All the deliverables}
151\end{figure}
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